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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Advanced UVM
      • Basic UVM
      • Introduction to UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

    • Additional Forums

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Low Power Verification - 4/29
      • Fault Campaign for Mixed-Signal - 5/4
      • User2User - 5/26
      • Webinar Calendar

    • On-Demand Webinars

      • CDC+RDC Analysis
      • Basic Abstraction Techniques
      • Safety Analysis Techniques
      • QVIP Workflow and Debug for PCIe
      • Writing a Proxy-driven Testbench
      • Achieving High Defect Coverage
      • Visualizer Features
      • All On-Demand Webinars

    • Recording Archive

      • Siemens EDA 2021 Functional Verification Webinar Series
      • Improving Your SystemVerilog & UVM Skills
      • Should I Kill My Formal Run?
      • Visualizer Debug Environment
      • Industry Data & Surveys
      • All Recordings

    • Conferences

      • DVCon 2021
      • DVCon 2020
      • DAC 2019
      • All Conferences

    • Mentor Learning Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

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    • Verification Horizons Publication

      • Verification Horizons - March 2021
      • Verification Horizons - November 2020
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    • Training

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Tag List

  • #systemverilog 533
  • #uvm 299
  • UVM 159
  • uvm 141
  • SVA 98
  • assertion 98
  • System Verilog 86
  • #systemverilog #ASSERTION 78
  • Assertions 70
  • Assertion system verilog 69
  • RAL 53
  • #UVM #RAL 53
  • #SVA 51
  • constraint 51
  • SystemVerilog 50
  • #systemverilog #Arrays 49
  • #randomization 48
  • #SystemVerilog #FunctionalCoverage 48
  • systemverilog 45
  • #coverage 39
  • DPI 38
  • #systemverilog #constraint 38
  • uvm_config_db 37
  • interface 34
  • constraint randomization 34
  • sequence 32
  • coverage 32
  • constraints 31
  • SVA Assertion 30
  • assert property 28
  • uvm_reg 26
  • scoreboard 26
  • #systemverilog #UVM 25
  • uvm_sequence 24
  • system verilog assertion SVA 24
  • cross coverage 24
  • class 24
  • ovm 24
  • randomization 24
  • #sequence 23
  • coverpoint 22
  • Inheritance 22
  • SV 22
  • clock 21
  • functional coverage 21
  • associative array 21
  • assertion systemverilog 21
  • Dynamic Array 20
  • Advanced UVM Register 20
  • config_db 19
  • virtual sequence 19
  • Package 19
  • covergroup 19
  • queue 19
  • ASSERTION BASED VERIFICATION 18
  • Formal Verification 18
  • #interface 18
  • analysis port 17
  • Web Seminar 17
  • bind 17
  • fork join 17
  • Verification Horizons 17
  • Verilog 17
  • virtual interface 17
  • $cast 17
  • OOPS 16
  • Learning System Verilog 16
  • Constraint random verification 16
  • array randomization 16
  • driver 16
  • mailbox 15
  • UVM phases 15
  • #systemverilog #Arrays #packedarrays #unpackedarrays 15
  • array 14
  • Constraint SystemVerilog 14
  • tlm 14
  • casting 14
  • #queues 14
  • task 14
  • sequencer 13
  • uvm register model 13
  • Polymorphism 13
  • Clocking Block 13
  • enum 13
  • uvm_info 13
  • VIP 13
  • system verilog assertion 12
  • Race condition 12
  • Seminar 12
  • questasim 12
  • factory 12
  • checker 12
  • parameter 12
  • wait statement 12
  • constrained random generation 12
  • BFM 11
  • questa 11
  • Randomize 11
  • uvm uvm_config_db 11
  • UVM Driver 11
  • randomization constraints 11
  • p_sequencer 11
  • assert 11
  • UVM_VERBOSITY 11
  • virtual sequencer 11
  • modport 11
  • Coverage bins 11
  • Cookbook: UVM 11
  • code coverage 11
  • Dave Rich 11
  • Portable Stimulus 11
  • macros 11
  • Bus interface 11
  • constraints systemverilog 10
  • string 10
  • $display 10
  • semaphore 10
  • dist 10
  • Verification 10
  • uvm_reg_block 10
  • VHDL 10
  • typedef 10
  • event 10
  • Cookbook: Phasing 10
  • functions in system verilog 10
  • uvm_config_db #(...)::get() 10
  • UVM uvm_test 10
  • uvm ral 10
  • #verilog 10
  • Event Regions 10
  • multiple agents 10
  • Cookbook: Scoreboards 9
  • generate block 9
  • dpi-c 9
  • uvm_driver 9
  • #uvm #verilog 9
  • #systemverilog #arrays #struct #constraint #randomization #indexes 9
  • #driver 9
  • for loop 9
  • fifo 9
  • backdoor 9
  • set_type_override_by_type 9
  • event trigger 9
  • Systemverilog Assertion 9
  • property 9
  • override 9
  • configuration 9
  • uvm_error 9
  • cross coverage bins 9
  • uvm_tlm_analysis_fifo 9
  • UVM monitor 9
  • for loop fork join_none 9
  • dynamic arrays 9
  • 2D array SystemVerilog 9
  • uvm_reg_map 9
  • systemverilog datatypes 9
  • generate 9
  • #queues #systemverilog 9
  • uvm_object 9
  • Assertions using Generate Block 8
  • uvm_component 8
  • sequences 8
  • agent 8
  • Constructor 8
  • configdb 8
  • Interfaces 8
  • introduction to system verilog 8
  • Use of virtual sequence and virtual sequencer. 8
  • UVM_PHASE 8
  • UVM Configuration database 8
  • randc 8
  • SOC verification 8
  • sequence and sequencer 8
  • Command Line Processing 8
  • system verilog constraints 8
  • uvm virtual interface 8
  • reset 8
  • Cookbook: Cookbook Code Examples 8
  • #systemverilog #ASSERTION #bind 8
  • uvm_mem 8
  • constraint array 8
  • function new 8
  • Parameters 8
  • fork join in loop 8
  • formal verification assertion 8
  • unpacked array 8
  • function 8
  • concurrent assertion 8
  • interface class 8
  • FATAL ERROR 8
  • class handle 8
  • accessing the associative array elements 8
  • field macros 8
  • systemc 8
  • uvm_sequence_item 8
  • disable fork 8
  • always_comb 7
  • Arbitration 7
  • Compilation Error 7
  • Cookbook: Registers 7
  • constraint dist 7
  • Polymorhphism 7
  • $realtime 7
  • static method 7
  • #OOP #polymorphism #MoveOperation #UVM 7
  • System Verilog Virtual Functions 7
  • TLM ports 7
  • I2C 7
  • comparator 7
  • coverage system verilog cover bins 7
  • Overridding parameterized class 7
  • Cookbook: Registers/ModelStructure 7
  • SVA checkers 7
  • UVM_reg_field 7
  • glitch 7
  • Debug 7
  • uvc 7
  • force signal 7
  • timing checks 7
  • TLM FIFO related 7
  • #error 7
  • modelsim 7
  • clone() 7
  • uvm_event 7
  • program block 7
  • argument pass by ref 7
  • uvm agent 7
  • $stable 7
  • Verification IP 7
  • classes 7
  • Verification Academy Technology Series 7
  • AMBA AXI 7
  • create() and new() 7
  • Checkers 7
  • actual interface 7
  • RAL register UVM 7
  • testbench 7
  • #configuration 7
  • Parameterized classes 7
  • #systemverilog interface 6
  • Transition Coverage. 6
  • uvm_reg_adapter 6
  • driver monitor 6
  • assertion coverage 6
  • uvm_hdl_force 6
  • build_phase 6
  • memory 6
  • registers 6
  • predict 6
  • #sequencer 6
  • uvm_analysis_imp 6
  • Questa® Formal Verification Apps 6
  • #systemverilog #enum #classes #constraints 6
  • Queues 6
  • UVM TLM Analysis port 6
  • UVM phase methods 6
  • generate macro `define 6
  • UVM callback 6
  • module 6
  • File reading 6
  • new function 6
  • deep copy 6
  • static 6
  • Delay 6
  • ASIC/IC Verification Trends 6
  • Real datatypes 6
  • error 6
  • SystemC UVMConnect 6
  • DUT 6
  • Extended Class 6
  • system verilog assertions 6
  • create macros or general functions 6
  • import 6
  • uvm register 6
  • uvm_report_server 6
  • $past 6
  • #fork_join 6
  • Active UVM models 6
  • UVM Sequence Library 6
  • Function new() 6
  • constraint foreach loop 6
  • Clock generator 6
  • array of covergroups 6
  • #uvm #factory 6
  • continuous assignment 6
  • system verilog testbench 6
  • real numbers 6
  • File I/O 6
  • #verifcation 6
  • #systemverilog DPI 6
  • constraint solver 6
  • start_item 6
  • constraints for random variables 6
  • Bins 6
  • fork join_none multiple threads 6
  • #ParameterizedClass 6
  • Advanced Verification 6
  • monitor 6
  • Cookbook: Coverage/Testplan to Functional Coverage 6
  • run_phase 6
  • SV systemVerilog constraints array 5
  • #uvm #callback 5
  • Streaming Operator 5
  • #0 event region 5
  • FSM 5
  • UVM Factory Registration 5
  • Constraining a random variable 5
  • function call 5
  • UVM MEMORY MODELING 5
  • Cookbook: Sequences/Slave 5
  • array slicing 5
  • Factory Overrides 5
  • Mirrored values and desired values in UVM RAL 5
  • enumeration datatype 5
  • Resource_db 5
  • Assertion binding 5
  • #UVM #virtual_sequences 5
  • semaphore keys 5
  • Cookbook: Driver/Pipelined 5
  • #bind 5
  • testcase 5
  • #coverage #exclusion 5
  • UVM_OBJECT and UVM_COMPONENT 5
  • forever loop/fork-join 5
  • RAL UVM adapter 5
  • Course 5
  • frontdoor 5
  • uvm_analysis_imp and uvm_analysis_export 5
  • uvm_monitor 5
  • run_phase() 5
  • functional verification 5
  • #uvm #config_db 5
  • CDC 5
  • set_inst_override 5
  • monitor to scoreboard 5
  • phase objection 5
  • uvm error 5
  • initialization 5
  • uvm_transaction 5
  • Cookbook: Registers/BackdoorAccess 5
  • Cookbook: Registers/SequenceExamples 5
  • sequencer and driver 5
  • Cookbook: Sequences/VirtualSequencer 5
  • sequence_item 5
  • fork join_any 5
  • uvm_do macros 5
  • unique 5
  • +uvm_set_severity 5
  • sequence body() 5
  • UVM Framework 5
  • Register abstraction Layer 5
  • illegal bins 5
  • start() in sequencer 5
  • functions 5
  • SVA Assertion Systemverilog 5
  • set_config_object 5
  • error injection 5
  • cover groups 5
  • parameterized 5
  • HDL designer systemverilog interface 5
  • AHB 5
  • Methodology 5
  • always blocks 5
  • #monitor 5
  • #UVM #RAL #systemverilog #ralmodelling 5
  • bitslice 5
  • assertion system verilog 5
  • parameterized class 5
  • sprint 5
  • AHB burst 5
  • #fork_joinnone 5
  • hierarchical reference 5
  • Null pointer dereference 5
  • #UVM #scoreboard 5
  • UVMConnect 5
  • DUT parameters 5
  • reference model 5
  • set_type_override 5
  • Virtual methods 5
  • Systemverilog DPI 5
  • uvm_warning 5
  • array interface parameterized 5
  • logic 4
  • UVM OBJECTIONS 4
  • timeout 4
  • timeunit 4
  • asynchronous 4
  • fork-join_none 4
  • get set 4
  • System Verilog Verilog File Read Operation 4
  • uvm_reg_predictor 4
  • connect sequencer 4
  • packed array 4
  • structure and union 4
  • random stability 4
  • Assertion property 4
  • syntax error 4
  • multidimensional array systemverilog 4
  • clock frequency 4
  • create 4
  • assert(std::randomize(variable)) 4
  • cross 4
  • uvm_factory 4
  • on the fly reset 4
  • reuse 4
  • #uvm_ral 4
  • #VHDL #SystemVerilog 4
  • Synchronization 4
  • first_match 4
  • compilation macro 4
  • wire 4
  • bus2reg 4
  • ignore_bins 4
  • #systemverilog#multidimentional arraya #memory 4
  • transactions 4
  • #UVM #Coverage 4
  • Low Power | UPF 4
  • Cookbook: Sequences/Stopping 4
  • assignment 4
  • uvm_reg frontdoor backdoor 4
  • DPI error 4
  • uvm_env 4
  • TLM 2.0 4
  • verification plan 4
  • UVM reuse 4
  • program 4
  • tlm_fifo 4
  • testbench environment 4
  • Multi-dimensional arrays 4
  • Pipelined 4
  • events 4
  • function coverage 4
  • system task 4
  • thread 4
  • LRM 4
  • fork 4
  • config 4
  • verbosity 4
  • Active Monitoring 4
  • SVA sequence 4
  • automatic variables 4
  • +uvm_set_inst_override 4
  • assertion errors 4
  • #APB 4
  • Infinite loop 4
  • systemverilog assertion concurrent 4
  • uvm sequence item 4
  • coverage transition bins 4
  • #event 4
  • Calling Sequence inside a sequence 4
  • array methods 4
  • $monitor 4
  • systemverilog randomization 4
  • Queues in system verilog 4
  • regression 4
  • Multiple Sequences 4
  • pass by reference 4
  • interface in system verilog 4
  • `uvm_do_with 4
  • randc usage constraint 4
  • master and slave 4
  • I2C protocol 4
  • initial_block 4
  • Sequence Layering 4
  • randomization error 4
  • synthesize 4
  • agents 4
  • Assign Delay 4
  • $rose 4
  • default_sequence 4
  • end of test mechanism in UVM 4
  • timing control 4
  • environment 4
  • uvm connect 4
  • inline constraints handling 4
  • Flow UVM 4
  • SV DPI 4
  • Non-blocking 4
  • regressions 4
  • multiple interface 4
  • constraints array-constraints 4
  • raise objection 4
  • Static function 4
  • fork join join_none 4
  • binding in SV 4
  • System-verilog 4
  • uvm_scoreboard 4
  • return data 4
  • cover property 4
  • Connect_Phase 4
  • sequence control 4
  • class override 4
  • inherited_classes 4
  • #clockingblock 4
  • inout 4
  • register layer 4
  • $fell 4
  • UVM system verilog 4
  • define struct 4
  • raise_objection and drop_objection 4
  • vcs 4
  • implication operator 4
  • SEED 4
  • Assertion : How to handle when delay in the signal. 4
  • #UVM_info 4
  • cover property SVA 4
  • UPF + power aware 4
  • GLS 4
  • compilation 4
  • register adapter 4
  • while 4
  • #delay uvm_components 4
  • Callbacks 4
  • Transaction 4
  • $fscanf 3
  • array of interfaces 3
  • mid test reset test sequence 3
  • non-consecutive repetition 3
  • regular expressions 3
  • mirrored value 3
  • raise_objection in pre_body() 3
  • System verilog for loop 3
  • simulation Terminate 3
  • task argument 3
  • Interface modport 3
  • UVM RAL UVM 3
  • multithreading 3
  • Delta-Delay Simulation and Unit-Delay Simulation 3
  • Cookbook: Agent 3
  • ternary 3
  • UVM Coverage 3
  • tlm port 3
  • systemtask 3
  • connect_phase in uvm 3
  • disable label 3
  • virtual 3
  • Inout port 3
  • if condition 3
  • shared object 3
  • system function 3
  • Assertion-Based Verification 3
  • pullup 3
  • Expression Coverage 3
  • #systemverilog#deepcopy 3
  • type_id::create() 3
  • sv env 3
  • UVM SystemVerilog 3
  • Cookbook: Sequences 3
  • Abstract interface 3
  • uvm_printer 3
  • SIGSEGV 3
  • ports 3
  • time 3
  • UCIS 3
  • Scheduling semantics in System Verilog 3
  • Related to UVM phases 3
  • timeout value 3
  • sequences and properties 3
  • end_tr 3
  • #logic 3
  • OVM Systemverilog 3
  • uvm_reg_adapter RAL 3
  • implementation 3
  • $throughout 3
  • hierarchical task call 3
  • always_ff 3
  • unexpected IDENTIFIER 3
  • adapter register 3
  • tasks 3
  • automatic 3
  • uvm_reg_sequence 3
  • Skew 3
  • UVM Configuration 3
  • Cookbook: Analysis 3
  • chris_hue 3
  • OOP 3
  • UVM Reporting 3
  • urandom 3
  • data flow synchronization 3
  • Parameter overriding 3
  • new 3
  • local variables 3
  • @(posedge clk) begin 3
  • Assertions $stable 3
  • division 3
  • #filewrite 3
  • Cookbook: Sequences/API 3
  • put_port 3
  • immediate assertion 3
  • simulation performance 3
  • reactive sequence 3
  • SVA Arbiter 3
  • $time 3
  • UVM RAL Backdoor Write hdl_path 3
  • `uvm_do 3
  • uvm_fatal 3
  • realtime 3
  • performance 3
  • test 3
  • Mapping data types 3
  • axi amba protocol 3
  • #signal_force 3
  • stuck between run_phase and extract_phase 3
  • Round-Robin Arbiter 3
  • #virtual 3
  • 2-dimensional dynamic array randomization 3
  • uvm interface 3
  • Multidimensional associative array; system verilog; exists method; array 3
  • parameterized interface 3
  • begin_tr 3
  • #endoftest 3
  • uvm_cmdline_processor 3
  • Harry Foster 3
  • UART 3
  • systemVerilog Queue Scoreboard UVM 3
  • Python Script 3
  • uvm overriding 3
  • Write 3
  • $root 3
  • UVM 1.2 3
  • Parent to an object 3
  • #hierarchy 3
  • Assignment inside generate block 3
  • Timescale issue 3
  • factory overriding at run time 3
  • interface connections 3
  • static property 3
  • assume 3
  • two clocks 3
  • reporting 3
  • fork join _none 3
  • predictor 3
  • delay timescale timeunit systemverilog 3
  • Modelling 3
  • Driver to scoreboard 3
  • `uvm_do_on 3
  • formal 3
  • convert 3
  • wait for change 3
  • UVM Reg model query 3
  • formal property verification 3
  • analysis port; connection;connect_phase 3
  • #UVM1.2 3
  • Blocking 3
  • uvm_sequence uvm_sequencer 3
  • #uvm_sequence 3
  • waveform 3
  • sequence arbitration 3
  • class issue 3
  • rounding 3
  • Assertion Multiple clocks 3
  • #system verilog #assertions #$past #$stable 3
  • compare 3
  • uvm_analysis_port 3
  • Questa® Power Aware Simulator 3
  • $assertoff 3
  • SystemVerilog Constructs 3
  • $display hierarchy 3
  • constraint for loop 3
  • SV constraint 3
  • behavioral model 3
  • uvm_phases 3
  • deep copy and shallow copy 3
  • Cookbook: Sequences/Hierarchy 3
  • accessing class variables in a loop 3
  • ral backdoor 3
  • #methods 3
  • clocking block; testbench 3
  • Generating sequences 3
  • UVM Questa 3
  • `define macro 3
  • DPI import 3
  • reading .txt file in UVM driver 3
  • passive agent 3
  • wait fork 3
  • cross coverage bins constraints 3
  • file 3
  • #UVMF 3
  • uvm_sequencer 3
  • SVA:$past 3
  • get_response 3
  • #skews 3
  • #array 3
  • uvm run_phase 3
  • API to access Ral model in OVM 3
  • Backdoor_access HDL access methods 3
  • c 3
  • $asserton 3
  • item 3
  • run_test(). 3
  • coverage ucdb 3
  • SV Constraint Solver 3
  • sv constraints 3
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