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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
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      • UVM Forum

    • SystemVerilog Forum

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      • SystemVerilog Forum

    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • DVClub Boston - July 31st
      • Mentor Forum for Verification - Bangalore 8/28 | Hyderabad 8/30
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
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Tag List

  • #systemverilog 274
  • uvm 142
  • #uvm 142
  • UVM 101
  • assertion 82
  • System Verilog 81
  • SVA 72
  • Assertions 56
  • RAL 51
  • Assertion system verilog 50
  • systemverilog 47
  • constraint 40
  • #SystemVerilog #FunctionalCoverage 35
  • uvm_config_db 35
  • DPI 33
  • #UVM #RAL 33
  • constraint randomization 32
  • interface 32
  • SystemVerilog 31
  • coverage 30
  • sequence 29
  • #systemverilog #Arrays 28
  • ovm 24
  • scoreboard 23
  • class 23
  • functional coverage 22
  • uvm_reg 21
  • uvm_sequence 21
  • system verilog assertion SVA 20
  • SVA Assertion 20
  • assertion systemverilog 20
  • assert property 19
  • Advanced UVM Register 19
  • cross coverage 19
  • randomization 18
  • SV 18
  • virtual sequence 18
  • constraints 18
  • queue 17
  • #randomization 17
  • Package 17
  • Dynamic Array 16
  • virtual interface 16
  • config_db 16
  • coverpoint 16
  • bind 15
  • Formal Verification 15
  • array randomization 15
  • Web Seminar 15
  • Learning System Verilog 14
  • OOPS 14
  • Inheritance 14
  • Constraint SystemVerilog 14
  • Verification Horizons 14
  • Verilog 14
  • associative array 14
  • mailbox 14
  • analysis port 14
  • Polymorphism 13
  • driver 13
  • task 13
  • $cast 12
  • Constraint random verification 12
  • system verilog assertion 12
  • parameter 12
  • sequencer 12
  • tlm 12
  • clock 12
  • virtual sequencer 11
  • UVM phases 11
  • p_sequencer 11
  • uvm_info 11
  • factory 11
  • systemc 11
  • Bus interface 11
  • code coverage 11
  • UVM uvm_test 11
  • covergroup 11
  • array 11
  • assert 11
  • Randomize 10
  • ASSERTION BASED VERIFICATION 10
  • uvm register model 10
  • VIP 10
  • constrained random generation 10
  • randomization constraints 10
  • Coverage bins 10
  • questasim 10
  • Portable Stimulus 10
  • Cookbook: UVM 10
  • #coverage 10
  • Clocking Block 9
  • Race condition 9
  • BFM 9
  • event trigger 9
  • modport 9
  • fork join 9
  • configuration 9
  • functions in system verilog 9
  • #uvm #verilog 9
  • dist 9
  • Seminar 9
  • uvm_tlm_analysis_fifo 9
  • property 9
  • VHDL 9
  • fifo 9
  • Cookbook: Phasing 9
  • uvm_config_db #(...)::get() 9
  • event 9
  • dpi-c 8
  • configdb 8
  • checker 8
  • uvm_error 8
  • Cookbook: Cookbook Code Examples 8
  • sequence and sequencer 8
  • multiple agents 8
  • #queues 8
  • uvm_reg_block 8
  • $display 8
  • dynamic arrays 8
  • Systemverilog Assertion 8
  • field macros 8
  • introduction to system verilog 8
  • system verilog constraints 8
  • class handle 8
  • questa 8
  • wait statement 8
  • unpacked array 8
  • uvm_driver 8
  • override 8
  • function 8
  • Verification 8
  • #systemverilog #Arrays #packedarrays #unpackedarrays 8
  • Event Regions 8
  • uvm_reg_map 8
  • uvm uvm_config_db 7
  • uvm virtual interface 7
  • uvm_mem 7
  • Verification Academy Technology Series 7
  • backdoor 7
  • casting 7
  • uvm_object 7
  • Checkers 7
  • constraints systemverilog 7
  • uvm_sequence_item 7
  • formal verification assertion 7
  • accessing the associative array elements 7
  • UVM_PHASE 7
  • UVM Driver 7
  • Dave Rich 7
  • UVM_VERBOSITY 7
  • static method 7
  • Cookbook: Registers/ModelStructure 7
  • SOC verification 7
  • Parameterized classes 7
  • concurrent assertion 7
  • Constructor 7
  • System Verilog Virtual Functions 7
  • reset 7
  • UVM Configuration database 7
  • agent 7
  • TLM FIFO related 7
  • 2D array SystemVerilog 7
  • Real datatypes 6
  • uvm_component 6
  • sequences 6
  • Questa® Formal Verification Apps 6
  • monitor 6
  • actual interface 6
  • Queues 6
  • UVM callback 6
  • constraint dist 6
  • create() and new() 6
  • Compilation Error 6
  • Arbitration 6
  • UVM monitor 6
  • uvm ral 6
  • Delay 6
  • RAL register UVM 6
  • generate 6
  • system verilog testbench 6
  • uvm_event 6
  • deep copy 6
  • import 6
  • uvm_analysis_imp 6
  • generate block 6
  • UVM Sequence Library 6
  • Cookbook: Scoreboards 6
  • registers 6
  • enum 6
  • vcs 6
  • assertion coverage 6
  • Parameters 6
  • Interfaces 6
  • FATAL ERROR 6
  • for loop 6
  • system verilog assertions 6
  • uvm_reg_adapter 6
  • interface class 6
  • Use of virtual sequence and virtual sequencer. 6
  • Overridding parameterized class 6
  • Debug 6
  • Clock generator 6
  • Cookbook: Coverage/Testplan to Functional Coverage 6
  • typedef 6
  • timing checks 6
  • constraint array 6
  • set_type_override_by_type 6
  • SystemC UVMConnect 6
  • Active UVM models 6
  • static 6
  • Cookbook: Registers 6
  • #verilog 6
  • sprint 5
  • classes 5
  • File I/O 5
  • enumeration datatype 5
  • Systemverilog DPI 5
  • error injection 5
  • always_comb 5
  • create macros or general functions 5
  • continuous assignment 5
  • UVM MEMORY MODELING 5
  • testbench 5
  • semaphore 5
  • Resource_db 5
  • hierarchical reference 5
  • +uvm_set_severity 5
  • run_phase 5
  • Flow UVM 5
  • reference model 5
  • Methodology 5
  • predict 5
  • Extended Class 5
  • start() in sequencer 5
  • clone() 5
  • constraint solver 5
  • parameterized 5
  • modelsim 5
  • array interface parameterized 5
  • uvm_transaction 5
  • UVMConnect 5
  • File reading 5
  • UVM_OBJECT and UVM_COMPONENT 5
  • real numbers 5
  • run_phase() 5
  • UVM Factory Registration 5
  • Register abstraction Layer 5
  • fork join in loop 5
  • Mirrored values and desired values in UVM RAL 5
  • set_inst_override 5
  • start_item 5
  • Transition Coverage. 5
  • uvm register 5
  • Constraining a random variable 5
  • UVM_reg_field 5
  • unique 5
  • Assertions using Generate Block 5
  • argument pass by ref 5
  • illegal bins 5
  • cover groups 5
  • macros 5
  • build_phase 5
  • driver monitor 5
  • function new 5
  • coverage system verilog cover bins 5
  • constraint foreach loop 5
  • set_type_override 5
  • module 5
  • program block 5
  • uvm agent 5
  • uvm_monitor 5
  • fork join_any 5
  • glitch 5
  • uvm_warning 5
  • uvc 5
  • systemverilog datatypes 5
  • functional verification 5
  • memory 5
  • Verification IP 5
  • Cookbook: Registers/SequenceExamples 5
  • constraints for random variables 5
  • uvm_sequencer 4
  • +uvm_set_inst_override 4
  • uvm_do macros 4
  • while 4
  • UVM system verilog 4
  • uvm_reg_predictor 4
  • compilation 4
  • tlm_fifo 4
  • UVM TLM Analysis port 4
  • fork join_none multiple threads 4
  • uvm_env 4
  • new function 4
  • transactions 4
  • implication operator 4
  • Cookbook: Driver/Pipelined 4
  • UVM reuse 4
  • Cookbook: Registers/BackdoorAccess 4
  • uvm_reg frontdoor backdoor 4
  • initialization 4
  • binding in SV 4
  • interface in system verilog 4
  • Course 4
  • Sequence Layering 4
  • Assertion binding 4
  • string 4
  • Infinite loop 4
  • Polymorhphism 4
  • packed array 4
  • Cookbook: Sequences/Slave 4
  • events 4
  • comparator 4
  • randc 4
  • SV DPI 4
  • wire 4
  • logic 4
  • ignore_bins 4
  • FSM 4
  • Queues in system verilog 4
  • return data 4
  • multiple interface 4
  • DUT 4
  • Command Line Processing 4
  • TLM ports 4
  • Cookbook: Sequences/Stopping 4
  • testbench environment 4
  • Factory Overrides 4
  • sequence body() 4
  • config 4
  • #error 4
  • assert(std::randomize(variable)) 4
  • bus2reg 4
  • Advanced Verification 4
  • function coverage 4
  • raise_objection and drop_objection 4
  • uvm_analysis_imp and uvm_analysis_export 4
  • RAL UVM adapter 4
  • AMBA AXI 4
  • generate macro `define 4
  • inout 4
  • cross 4
  • #uvm #callback 4
  • System Verilog Verilog File Read Operation 4
  • randomization error 4
  • array methods 4
  • Low Power | UPF 4
  • array slicing 4
  • automatic variables 4
  • timeout 4
  • timeunit 4
  • inherited_classes 4
  • SEED 4
  • UPF + power aware 4
  • UVM phase methods 4
  • cover property 4
  • LRM 4
  • Xilinx 4
  • frontdoor 4
  • $realtime 4
  • sequence control 4
  • DPI import 4
  • reuse 4
  • sequencer and driver 4
  • synthesize 4
  • structure and union 4
  • cross coverage bins 4
  • register adapter 4
  • on the fly reset 4
  • regressions 4
  • uvm_factory 4
  • array of covergroups 4
  • end of test mechanism in UVM 4
  • coverage transition bins 4
  • error 4
  • first_match 4
  • gcc 4
  • Multiple Sequences 4
  • uvm connect 4
  • for loop fork join_none 4
  • uvm error 4
  • set_config_object 4
  • Abstract interface 3
  • Cookbook: Analysis 3
  • array of defines 3
  • $root 3
  • assert #0 3
  • passive agent set_drain_time 3
  • thread 3
  • $stable 3
  • master and slave 3
  • static variable 3
  • performance 3
  • OVM Systemverilog 3
  • simulation performance 3
  • Streaming Operator 3
  • uvm_object_utils 3
  • Timescale issue 3
  • Callbacks 3
  • UVM Reporting 3
  • derived class 3
  • waveform 3
  • Cookbook: Registers/StimulusAbstraction 3
  • UCIS 3
  • task argument 3
  • #uvm #factory 3
  • SV constraint 3
  • Wilson Research Group Study 3
  • interface connections 3
  • class issue 3
  • uvm overriding 3
  • Parent to an object 3
  • Blocking 3
  • SVA checkers 3
  • reporting 3
  • pass by reference 3
  • grab regmodel sequencer 3
  • UVM raise and drop objection 3
  • SIGSEGV 3
  • Multi-dimensional arrays 3
  • clocking block event 3
  • c 3
  • delay timescale timeunit systemverilog 3
  • functions 3
  • uvm_printer 3
  • type_id::create() 3
  • always_ff 3
  • singleton class 3
  • sequences and properties 3
  • memory verification 3
  • UVM Coverage 3
  • multithreading 3
  • I2C 3
  • fork 3
  • Cookbook: Testbench/Blocklevel 3
  • SV Constraint Solver 3
  • uvm_reg_sequence 3
  • get_config_object 3
  • Virtual methods 3
  • class override 3
  • array interface in uvm_config_db 3
  • System-verilog 3
  • Write 3
  • shallow copy 3
  • UVM Predictor UVM_REG_MAP 3
  • end_tr 3
  • #delay uvm_components 3
  • `uvm_do_with 3
  • agents 3
  • systemverilog mailbox 3
  • Connect_Phase 3
  • initial_block 3
  • tlm port 3
  • CDC 3
  • Analog behavioral model 3
  • Null Object Access 3
  • UVM SystemVerilog 3
  • mirrored value 3
  • chris_hue 3
  • assume 3
  • Questa® Power Aware Simulator 3
  • SVA Arbiter 3
  • uvm_field_int 3
  • shared object 3
  • $monitor 3
  • main_phase 3
  • raise objection 3
  • reading .txt file in UVM driver 3
  • C++ 3
  • AHB 3
  • hierarchical task call 3
  • uvm run_phase 3
  • constraint for loop 3
  • Null pointer dereference 3
  • force signal 3
  • mid test reset test sequence 3
  • randc usage constraint 3
  • get set 3
  • Bind Factory UVM 3
  • system verilog module 3
  • VIP integration 3
  • uvm_report_server 3
  • register layer 3
  • EDA Playground 3
  • parameterized class 3
  • convert 3
  • get_response 3
  • Cookbook: Config/ConfiguringSequences 3
  • $display hierarchy 3
  • $past 3
  • program 3
  • implementation 3
  • DPI error 3
  • UVM1.1d documentation source code 3
  • UVM RAL Backdoor Write hdl_path 3
  • Harry Foster 3
  • SystemVerilog Constructs 3
  • axi amba protocol 3
  • environment 3
  • AHB burst 3
  • finish_item 3
  • connect_phase in uvm 3
  • #reset 3
  • Calling Sequence inside a sequence 3
  • wait_modified() 3
  • #SVA 3
  • UVM sequence UVM hierachy 3
  • SCE-MI for Co-Emulation 3
  • Cookbook: Sequences/VirtualSequencer 3
  • compare 3
  • fork join join_none 3
  • virtual 3
  • uvm_scoreboard 3
  • UPF 3
  • randomize with 3
  • `define macro 3
  • systemverilog assertion concurrent 3
  • UVM 1.2 3
  • raise_objection in pre_body() 3
  • uvm_phases 3
  • uvm_cmdline_processor 3
  • UVM Configuration 3
  • TLM 2.0 3
  • begin_tr 3
  • #systemverilog DPI 3
  • Assertion-Based Verification 3
  • Questasim 10.0b 3
  • sv env 3
  • Abstract class 3
  • UVM OBJECTIONS 3
  • asynchronous 3
  • factory overriding at run time 3
  • uvm_hdl_force 3
  • #configuration 3
  • enumerated 3
  • ASIC/IC Verification Trends 3
  • non static method 3
  • Mapping data types 3
  • static property 3
  • Function new() 3
  • UVM Register Built-in sequence 3
  • verbosity 3
  • pullup 3
  • timeout value 3
  • systemVerilog Queue Scoreboard UVM 3
  • uvm register w1c 3
  • put_port 3
  • Cookbook: Questa/CompilingUVM 3
  • Generating sequences 3
  • Cookbook: Sequences/Hierarchy 3
  • API to access Ral model in OVM 3
  • test 3
  • local variables 3
  • parameterized interface 3
  • get_next_item 3
  • Cookbook: Agent 3
  • urandom 3
  • $fell 3
  • cover property SVA 3
  • passive agent 3
  • Non-blocking 3
  • signed 3
  • assertion ##1 3
  • HDL designer systemverilog interface 3
  • assertion errors 3
  • Pipelined 3
  • stuck between run_phase and extract_phase 3
  • ucdb 3
  • DUT parameters 3
  • #systemverilog#deepcopy 3
  • questa formal 3
  • ports 3
  • cross coverage bins constraints 3
  • System verilog for loop 3
  • fork join_any fork join_none 3
  • Expression Coverage 3
  • uvm_sequence uvm_sequencer 3
  • Questasim for VHDL 2
  • register read() mirror set_check_on_read 2
  • unpacked array of packed array 2
  • associative array inline constraint 2
  • Efficient way to cross transition cover points 2
  • Interface clocking block 2
  • specman 2
  • iff 2
  • uvm_driver uvm system_verilog 2
  • randomisation 2
  • parameterized interfaces parameter interface system verilog 2
  • Get_next_item called twice without item_done or get in between 2
  • Nested class 2
  • Test-plan 2
  • within 2
  • uvm_sv_unit 2
  • parametrization 2
  • block level testcase 2
  • Access Verilog Array in Uvm classs 2
  • $fscanf 2
  • Conditional constraint 2
  • uvm_heartbeat 2
  • arrays 2
  • do_not_randomize 2
  • grab 2
  • active/passive agent configuration 2
  • shuffle 2
  • SVA sequence 2
  • Interrupt service routine 2
  • non-virtual 2
  • Burst access using RAL 2
  • `uvm_do 2
  • signed arithmetic 2
  • UVMC 2
  • systemverilog checker 2
  • RACE 2
  • SVUnit 2
  • vcoVER MERGE 2
  • Assertion : How to handle when delay in the signal. 2
  • Driver Class-Generator Class 2
  • agent configuration file 2
  • multiple 2
  • AXI VIP 2
  • coverage ucdb 2
  • connect sequencer 2
  • #packed array and queues 2
  • RTL 2
  • item_done 2
  • phase_drop_objection 2
  • simulation time 2
  • multiple environment uvm 2
  • #signal_force 2
  • runtime speed 2
  • UVM COMMANDLINE PROCESSOR 2
  • Cookbook: Registers/AdapterContext 2
  • strong typing rules 2
  • Code Coverage waivers 2
  • indirect_addressing 2
  • timing control 2
  • package - import usage in environment arch. 2
  • system verilog analogue port real types 2
  • #systemverilog #Arrays logics 2
  • slow 2
  • uvm_config_db uvm_resource_db 2
  • Generic clock generation 2
  • Sequential sequence 2
  • Method Overriding 2
  • #systemverilog#multidimentional arraya #memory 2
  • Cookbook: Sequences/LockGrab 2
  • event scheduling 2
  • uvm_reg_bit_bash_seq 2
  • analysis port; connection;connect_phase 2
  • get 2
  • forever loop/fork-join 2
  • mirror value 2
  • Assign Delay 2
  • socket connection 2
  • NBA 2
  • ELBERR: Error during elaboration (status 1) 2
  • parameterized macro 2
  • bit slice in force syntax 2
  • abstract monitor 2
  • online course 2
  • concatenation 2
  • regular expressions 2
  • UVM_FATAL @ 0: reporter [BUILDERR] 2
  • array of interfaces 2
  • global 2
  • queue array 2
  • uvm_top.find() 2
  • #APB 2
  • clock frequency 2
  • do_print 2
  • signal 2
  • $root access from within packages is not allowed 2
  • mailbox error 2
  • static constructor 2
  • BURST Transfer AHB 2
  • `uvm_do_on 2
  • UVMC Compilation 2
  • sequence killed or finished 2
  • uvm randomization 2
  • uvm automated testbench 2
  • protocol checks using assertions 2
  • Period 2
  • ovm uvm 2
  • uvm_analysis_export 2
  • UVM register mapping pages 2
  • ral backdoor 2
  • verification concepts 2
  • connection 2
  • push_pull 2
  • Cookbook: OVM/Phasing 2
  • phase_raise_objection 2
  • drop objection 2
  • include 2
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