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The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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#systemverilog 728
#uvm 328
UVM 229
uvm 141
#systemverilog #ASSERTION 116
SVA 109
assertion 108
#SVA 94
System Verilog 93
#constraint #randomization 88
Assertions 84
SystemVerilog 77
#coverage 76
#System verilog 75
Assertion system verilog 74
#systemverilog #Arrays 66
#randomization 64
RAL 59
#UVM #RAL 59
#SystemVerilog #FunctionalCoverage 58
constraint 57
#systemverilog #UVM 56
#systemverilog #constraint 48
#sequence 45
systemverilog 44
coverage 40
DPI 40
uvm_config_db 39
interface 38
#assertion 38
constraint randomization 35
constraints 34
sequence 32
coverpoint 32
SVA Assertion 31
assert property 31
#interface 30
cross coverage 29
#systemverilog #Arrays #packedarrays #unpackedarrays 29
scoreboard 28
Inheritance 28
SV 27
randomization 26
associative array 26
uvm_reg 26
class 26
Dynamic Array 25
Package 24
uvm_sequence 24
ovm 24
system verilog assertion SVA 24
#coverage #bins 23
functional coverage 23
#queues #systemverilog 23
clock 23
#UVM #scoreboard 23
$cast 23
Verilog 23
Formal Verification 22
#queues 21
assertion systemverilog 21
covergroup 21
virtual sequence 20
#array 20
Advanced UVM Register 20
#systemverilog #arrays #struct #constraint #randomization #indexes 19
fork join 19
analysis port 19
enum 19
config_db 19
queue 19
bind 19
array randomization 18
ASSERTION BASED VERIFICATION 18
virtual interface 18
uvm register model 18
#RAL #UVM 18
casting 18
OOPS 18
Clocking Block 17
Web Seminar 17
Verification Horizons 17
array 17
Constraint random verification 16
Learning System Verilog 16
driver 16
Race condition 16
mailbox 16
UVM Driver 15
BFM 15
uvm ral 15
Polymorphism 15
#uvm #sv #constraints 15
#driver 15
task 15
p_sequencer 15
UVM phases 15
tlm 14
#logic 14
VIP 14
#systemverilog #ASSERTION #bind 14
Cookbook: UVM 14
checker 14
Constraint SystemVerilog 14
Constructor 14
sequencer 13
Systemverilog Assertion 13
semaphore 13
fifo 13
#ParameterizedClass 13
Coverage bins 13
#RAL 13
wait statement 13
#fork_join 13
system verilog assertion 13
factory 13
#system verilog #assertions #$past #$stable 13
#UVM #RAL #systemverilog #ralmodelling 13
system verilog constraints 13
parameter 13
uvm_info 13
modport 12
#verilog 12
#error 12
uvm_config_db #(...)::get() 12
cross coverage bins 12
uvm_reg_block 12
UVM monitor 12
assert 12
force signal 12
uvm_reg_map 12
virtual sequencer 12
Randomize 12
uvm uvm_config_db 12
#uvm #uvm_config_db 12
Seminar 12
constrained random generation 12
generate 11
systemc 11
#Assertions #clock 11
VHDL 11
UVM_VERBOSITY 11
class handle 11
$display 11
macros 11
Bus interface 11
#uvm #factory 11
dynamic arrays 11
Dave Rich 11
questasim 11
dist 11
string 11
AMBA AXI 11
#sequencer 11
UVM uvm_test 11
questa 11
event 11
#Systemverilog #UVM #RAL 11
for loop fork join_none 11
uvm_driver 11
Verification 11
#systemverilog #enum #classes #constraints 11
# UVM #ASSERTIONS #CADENCE 11
#systemverilog interface 11
uvm_mem 11
UVM_PHASE 11
Portable Stimulus 11
#uvm #config_db 11
code coverage 11
Cookbook: Phasing 10
#uvm_reg 10
uvm_error 10
Debug 10
build_phase 10
#OOP #polymorphism #MoveOperation #UVM 10
agent 10
SVA Assertion Systemverilog 10
typedef 10
for loop 10
constraint dist 10
2D array SystemVerilog 10
multiple agents 10
UVM Configuration database 10
set_type_override_by_type 10
override 10
#uvm_config_db 10
Checkers 10
functions in system verilog 10
constraints systemverilog 10
backdoor 10
#transition #coverage #cross #bins #ignore_bins 10
uvm_tlm_analysis_fifo 10
FATAL ERROR 10
randomization constraints 10
dpi-c 10
Event Regions 10
Assertions using Generate Block 9
generate block 9
Use of virtual sequence and virtual sequencer. 9
get_response 9
uvm virtual interface 9
configuration 9
Cookbook: Registers 9
event trigger 9
#uvm_sequence 9
uvm_component 9
concurrent assertion 9
uvm_event 9
#systemverilog #distribution #constraints 9
disable fork 9
uvm_object 9
Cookbook: Scoreboards 9
property 9
#systemverilog #class #event 9
#uvm #verilog 9
systemverilog datatypes 9
function 9
Interfaces 9
configdb 8
reference model 8
#uvm #uvm_driver # 8
sequences 8
uvm_sequence_item 8
function new 8
Polymorhphism 8
randc 8
Cookbook: Cookbook Code Examples 8
#clockingblock 8
introduction to system verilog 8
UVM_reg_field 8
SVA checkers 8
constraint foreach loop 8
fork join in loop 8
field macros 8
classes 8
Parameters 8
RTL 8
interface class 8
sequence and sequencer 8
ASIC/IC Verification Trends 8
clone() 8
uvc 8
formal verification assertion 8
unpacked array 8
$stable 8
RAL register UVM 8
#sequence item 8
accessing the associative array elements 8
error 8
timing checks 8
monitor 8
#class 8
#monitor 8
SOC verification 8
uvm sequence item 8
comparator 8
Compilation Error 8
#systemverilog DPI 8
program block 8
constraint array 8
module 8
reset 8
Command Line Processing 8
compilation macro 8
File I/O 7
system verilog assertions 7
#systemverilog #Strings 7
#UVMF 7
#base_test #uvm_tlm_fifo 7
memory 7
create macros or general functions 7
TLM ports 7
UVM callback 7
coverage system verilog cover bins 7
#UVM_info 7
System Verilog Virtual Functions 7
#Testbench 7
static method 7
#uvm #testbench #verification 7
argument pass by ref 7
parameterized class 7
#reset 7
Backdoor_access HDL access methods 7
#uvm #callback 7
set_type_override 7
wire 7
generate macro `define 7
TLM FIFO related 7
Parameterized classes 7
static 7
Real datatypes 7
create() and new() 7
SV systemVerilog constraints array 7
Delay 7
Arbitration 7
File reading 7
Assertion property 7
Overridding parameterized class 7
modelsim 7
sequence body() 7
actual interface 7
#configuration 7
Cookbook: Registers/ModelStructure 7
always_comb 7
import 7
testbench 7
Verification IP 7
$realtime 7
UVM TLM Analysis port 7
run_phase 7
start_item 7
uvm agent 7
#covergroup 7
Queues 7
Verification Academy Technology Series 7
#UVM #virtual_sequences 7
#uvm_ral 7
#verifcation 7
glitch 7
Cookbook: Driver/Pipelined 7
predict 6
uvm_env 6
AHB burst 6
UVM Sequence Library 6
testcase 6
Cookbook: Registers/SequenceExamples 6
UVM system verilog 6
Extended Class 6
registers 6
timeout 6
#systemverilog #Arrays logics 6
DPI error 6
uvm_factory 6
systemverilog mailbox 6
$past 6
UVM OBJECTIONS 6
uvm_hdl_force 6
Clock generator 6
Cookbook: Sequences/VirtualSequencer 6
#FunctionArgument 6
Function new() 6
enumeration datatype 6
assume 6
cross bins 6
assertion coverage 6
#parameter 6
uvm_analysis_imp 6
#0 event region 6
FSM 6
get_next_item 6
Active UVM models 6
Questa® Formal Verification Apps 6
#coverage #exclusion 6
Bins 6
automatic variables 6
#systemverilog #coverage 6
illegal bins 6
constraint solver 6
uvm_report_server 6
assertion system verilog 6
constraints for random variables 6
driver monitor 6
coverage transition bins 6
semaphore keys 6
continuous assignment 6
UVM RAL UVM 6
#bind 6
uvm error 6
I2C 6
functions 6
Null pointer dereference 6
#UVM #DRIVER #INTERFACE 6
UVM Reporting 6
fork join_none multiple threads 6
#override 6
#uvm #factory #override 6
UVMConnect 6
$random 6
new function 6
UVM phase methods 6
SystemC UVMConnect 6
#virtual 6
uvm register 6
Related to UVM phases 6
DUT 6
Cookbook: Coverage/Testplan to Functional Coverage 6
unique 6
UPF + power aware 6
compilation 6
system verilog testbench 6
Low Power | UPF 6
#UVM #Coverage 6
deep copy 6
fork 6
uvm_reg_adapter 6
first_match 6
LRM 6
Cookbook: Sequences/Slave 6
CDC 6
#fork_joinnone 6
real numbers 6
UVM Framework 6
AHB 6
UVM MEMORY MODELING 6
#delay uvm_components 6
#RAL #UVM #PREDICTOR 6
array of covergroups 6
#clockgeneraation 6
#system verilog #coverage #with clause #coverpoints 6
Advanced Verification 6
uvm_do macros 5
uvm scorebaord 5
Systemverilog DPI 5
#polymorphism# 5
ignore_bins 5
$monitor 5
hierarchical reference 5
Register abstraction Layer 5
Constraining a random variable 5
set_config_object 5
assert(std::randomize(variable)) 5
fork join_any 5
#System verilog #interface 5
cross 5
cover groups 5
#packed array and queues 5
ifdef 5
Methodology 5
Queues in system verilog 5
phase objection 5
UART 5
monitor to scoreboard 5
functional verification 5
Assertion : How to handle when delay in the signal. 5
$assertoff 5
Streaming Operator 5
initialization 5
multidimensional array systemverilog 5
constraints array-constraints 5
clock frequency 5
#associative_arrays 5
start() in sequencer 5
#uvm # sequence 5
synthesis 5
Factory Overrides 5
DUT parameters 5
UVM Factory Registration 5
cover property SVA 5
sequencer and driver 5
new 5
bitslice 5
always blocks 5
events 5
uvm_analysis_imp and uvm_analysis_export 5
#systemverilog#multidimentional arraya #memory 5
register adapter 5
function call 5
sequence arbitration 5
uvm uvm_reg 5
run_phase() 5
Transition Coverage. 5
Assertion binding 5
randomize with 5
sequence_item 5
frontdoor 5
Cookbook: Sequences/LockGrab 5
#run_phase 5
uvm_warning 5
forever loop/fork-join 5
inherited_classes 5
HDL designer systemverilog interface 5
VPI 5
Cookbook: Registers/BackdoorAccess 5
#systemverilog #driver #monitor #virtual interface #transaction 5
#event 5
uvm_agent 5
array methods 5
sprint 5
simulation performance 5
thread 5
array slicing 5
environment 5
OOP 5
#uvm #dynamicarray 5
fork-join_none 5
inout 5
SEED 5
Connect_Phase 5
uvm_monitor 5
uvm_callback 5
UVM_OBJECT and UVM_COMPONENT 5
Synchronization 5
Assign Delay 5
set_inst_override 5
adapter register 5
+uvm_set_inst_override 5
I2C protocol 5
Virtual methods 5
#uvm #sequence #test 5
asynchronous 5
Course 5
error injection 5
$fell 5
Resource_db 5
Mirrored values and desired values in UVM RAL 5
parameterized 5
array interface parameterized 5
uvm_scoreboard 5
uvm connect 5
System-verilog 5
#signal_force 5
Transaction 5
uvm_transaction 5
+uvm_set_severity 5
uvm_reg frontdoor backdoor 5
binding in SV 4
randomization error 4
Inout port 4
Calling Sequence inside a sequence 4
Ethernet 4
array bins 4
uvm_reg_sequence 4
wait fork 4
get set 4
logic 4
compare 4
Priority 4
#eventtrigger 4
Abstract class 4
System Verilog Verilog File Read Operation 4
sysyem verilog 4
convert 4
Active Monitoring 4
syntax error 4
default_sequence 4
timeunit 4
assertion ##1 4
uvm register w1c 4
pullup 4
delay timescale timeunit systemverilog 4
formal 4
$countones 4
class override 4
automatic 4
#create 4
formal property verification 4
testbench environment 4
#systemverilog #generate 4
finish_item 4
event scheduling 4
systemverilog randomization 4
Cookbook: Sequences/Hierarchy 4
array of interfaces 4
backdoor read_wrie 4
master and slave 4
Non-blocking 4
interface in system verilog 4
#implication 4
Cookbook: Code Example Downloads 4
forever block 4
Golden Reference Model 4
Null Object Access 4
Infinite loop 4
TLM 2.0 4
cover property 4
System Verilog Basics 4
tlm_fifo 4
$rose 4
#systemverilog #syntax 4
multiple interface 4
#factory 4
#APB 4
UVM Coverage 4
register layer 4
analysis port; connection;connect_phase 4
sytemverilog 4
concatenation 4
randc usage constraint 4
Timescale 4
fork join join_none 4
define struct 4
#model #uvm #reference_model 4
system function 4
config 4
random stability 4
systemverilog assertion concurrent 4
#system verilog #sum# 4
#UVM #TLM Port_Export 4
on the fly reset 4
DPI import 4
reuse 4
verification plan 4
Pipelined 4
Multiple Sequences 4
end of test mechanism in UVM 4
non-consecutive repetition 4
active/passive agent configuration 4
transactions 4
Timescale issue 4
tasks 4
cross coverage bins constraints 4
Multi-dimensional arrays 4
if condition 4
initial_block 4
verbosity 4
structure and union 4
Write 4
#RAL #efficient 4
UPF 4
Clock Generation 4
data flow synchronization 4
#FIFO #UVM #VIRTUAL INTERFACE 4
Driver sequencer Handshake 4
Flow UVM 4
program 4
base class 4
uvm_cmdline_processor 4
#asynchronous 4
arrays 4
GLS 4
pass by reference 4
SV Constraint Solver 4
bus2reg 4
regression 4
while 4
C++ 4
UVM reuse 4
assertion errors 4
inline constraints handling 4
#uvm #packed #unpacked #array #SV 4
raise_objection and drop_objection 4
$readmemh 4
connect sequencer 4
uvm_analysis_port 4
reactive sequence 4
systemc verification 4
assign 4
coverpoint sample 4
assignment 4
copy method 4
run_test(). 4
create 4
Sequence Layering 4
synthesize 4
#Move #Memory #Class 4
timing control 4
system task 4
agents 4
binsof() 4
Cookbook: Sequences 4
#task 4
analysis export 4
RAL UVM adapter 4
#hierarchy 4
time 4
sequence control 4
extern task of a class 4
SV DPI 4
Static function 4
regressions 4
ternary 4
packed array 4
dynamic array constraint 4
Callbacks 4
performance 4
vcs 4
uvm_event_pool 4
EDA Playground 4
signed 4
uvm_reg_predictor 4
return data 4
SVA sequence 4
parameterized interface 4
Assertion-Based Verification 4
Cookbook: Sequences/Stopping 4
accessing class variables in a loop 4
foreach 4
`uvm_do_with 4
hang 3
test 3
library 3
fork_join 3
#packed 3
multi-threading 3
SVA Arbiter 3
Method Overriding 3
2-dimensional dynamic array randomization 3
argument 3
uvm message reporting 3
tlm port 3
multiple 3
local variables 3
signed arithmetic 3
#python 3
uvm_hdl_deposit 3
systemVerilog Queue Scoreboard UVM 3
$root 3
Clock domain crossing 3
instantiation vs inheritance 3
urandom 3
uvm_analysis_export 3
verilog blocking assignments 3
array of defines 3
item 3
Multiple requests 3
connect_phase in uvm 3
SVA:$past 3
$throughout 3
#test #uvm #coverage # 3
Driver to scoreboard 3
uvm_monitor; uvm_scoreboard; write(); 3
throughout 3
macro 3
interface connections 3
transaction class 3
uvm_comparer 3
enumeration 3
include 3
conditional 3
sv dpi export 3
random 3
clone 3
Cookbook: Driver/Sequence API 3
Application of Factory Overrides 3
prediction monitor scoreboard 3
UVMC 3
UVM sine wave 3
sequences and properties 3
AXI VIP 3
@(posedge clk) begin 3
questa formal 3
Blocking 3
immediate assertion 3
get_config_object 3
#0 delays 3
item_done 3
UVM Predictor UVM_REG_MAP 3
NOA 3
implementation 3
waveform 3
#for loop 3
Assertions $stable 3
$time 3
UVM raise and drop objection 3
uvm_test 3
modport clocking block 3
#assignment 3
matlab 3
#skews 3
systemtask 3
multithreading 3
beginner 3
clocking block; testbench 3
#virtual_interface 3
division 3
uvm_phases 3
timeout value 3
ports 3
sv env 3
layered sequence 3
#methods 3
Vivado 3
Memory management 3
random seeds regression 3
fork join_any fork join_none 3
internal signal in DUT 3
Wilson Research Group Study 3
Bind Factory UVM 3
Harry Foster 3
SCE-MI for Co-Emulation 3
uvm scoreboard methodology 3
soft constraints; hard constraints; constraints 3
do_copy uvm_sequence_item 3
predictor 3
Automatic Function 3
UVM1.1d documentation source code 3
UVM sequence UVM hierachy 3
uvm backdoor register model 3
uvm_fatal 3
#DPI-C 3
hierarchical task call 3
assertion synthesis checker SystemVerilog 3
Cookbook: Registers/StimulusAbstraction 3
Abstract interface 3
UVM SystemVerilog 3
#systemverilog#deepcopy 3
OVL_SVA 3
uvm print 3
disable assertion 3
sensitivity list 3
export DPI-C 3
broadcast writes 3
extended transaction 3
Parent to an object 3
#unsigned 3
clocking block assignment 3
begin_tr 3
Cookbook: UVM/Guidelines 3
Cookbook: Config/ConfiguringSequences 3
clocking blocks 3
`UVM_INFO component name meaningless 3
associative 3
realtime 3
counter example 3
reporting 3
$asserton 3
shallow copy 3
NBA 3
Cookbook: OVM/Phasing 3
$display hierarchy 3
shuffle 3
put_port 3
AHB protocol testbench code 3
PERL 3
mid test reset test sequence 3
axi amba protocol 3
mirror value 3
genvar 3
Parameter overriding 3
array covergroup functional coverage 3
SIGSEGV 3
instance 3
system verilog module 3
multiple drivers 3
upcasting 3
Cookbook: Reporting/Verbosity 3
ral backdoor 3
array manipulation methods 3
Questa inFact 3
sequncer 3
wait_modified() 3
Modelling 3
UART VIP 3
simulation Terminate 3
Xilinx 3
UVM Configuration 3
Analog behavioral model 3
clock synchronous 3
`define 3
clocking block event 3
singleton class 3
#VHDL #SystemVerilog 3
reading .txt file in UVM driver 3
SV constraint 3
VIP integration 3
randcase 3
UVM Reg model query 3
regular expressions 3
regmodel 3
static property 3
chris_hue 3
stimulus in system verilog 3
shared object 3
uvm_do_with 3
SystemVerilog Constructs 3
#systemverilog #assignment-like 3
two clocks 3
#passbyreference 3
derived class 3
#datatype 3
SVA Assertion Systemverilog 3
#uvm #package 3
$fscanf 3
Specific randomization in system verilog class 3
#dynamic 3
raise objection 3
SPI 3
hierarchy 3
uvm_sequence uvm_sequencer 3
coverage ucdb 3
main_phase 3
$system 3
dave_rich 3
implication assertion 3
get_next_item handshaking uvm 3
components in VIP 3
$urandom 3
#uvm_sequence_item 3
`define macro 3
`uvm_do 3
uvm_object_utils 3
behavioral model 3
copy 3
functional coverage systemverilog 3
Questa® Power Aware Simulator 3
UVM Error : 3
#lowertrianglematrix #systemverilog #constraint 3
factory overriding at run time 3
grab regmodel sequencer 3
class issue 3
UVM 1.2 3
Scheduling semantics in System Verilog 3
architecture 3
Python Script 3
sequencer arbitration 3
Multidimensional associative array; system verilog; exists method; array 3
$FWRITE 3
print 3
System verilog for loop 3
uvm_field_int 3
uvm overriding 3
#RAL #IPXACT 3
Case statement in sv 3
uvm_sequencer 3
#registers 3
#fileread 3
connectivity using SVA 3
Cookbook: Sequences/Overrides 3
simulation time 3
disable label 3
#fork_joinany 3
constarint 3
Expression Coverage 3
function coverage 3
$urandom_range 3
UVM RAL Backdoor Write hdl_path 3
Cookbook: UVM Connect 3
sv assertion 3
Cookbook: Agent 3
#virtual interface #scoreboard #uvm 3
Interface modport 3
systemverilog #checkers 3
uvm_packer 3
virtual 3
static constructor 3
default value 3
uvm events synchronisation 3
#UVM #RAL #BACKDOOR 3
associative array methods 3
static variable 3
error in class extension specification 3
uvm run_phase 3
object 3
VCD 3
uvm interface 3
file 3
Delta-Delay Simulation and Unit-Delay Simulation 3
Generating sequences 3
string concatenation 3
Formal Coverage 3
Assertion Multiple clocks 3
#property 3
phase_raise_objection 3
mirrored value 3
raise_objection in pre_body() 3
array interface in uvm_config_db 3
UVM package compile 3
#UVM1.2 3
always_ff 3
mixed UVM OVM 3
$sformatf 3
type_id::create() 3
#filewrite 3
UVM_BACKDOOR 3
Accellera Portable Stimulus Standard 3
compiler directive 3
Round-Robin Arbiter 3
UVM Questa 3
get_registers method for uvm_reg_block 3
$value$plusargs 3
OVM Systemverilog 3
#AXI 3
task argument 3
Cookbook: Analysis 3
#virtual key word 3
`uvm_do_on 3
deep copy and shallow copy 3
distribution 3
apb 3
constraint for loop 3
Copy() 3
functional coverages 3
uvm_printer 3
passive agent 3
#UVM #Component #UVMTemplates #ReferenceDesign #UVMF 3
wildcard 3
timing regions 3
PCIe 3
memory verification 3
assertion clock sync 3
API to access Ral model in OVM 3
uvm_reg_adapter RAL 3
wire logic 3
#package #variable #uvm 3
#uvm #parameter #uvm_subscriber 3
bit slicing 3
wait for change 3
#endoftest 3
stuck between run_phase and extract_phase 3
# UVM #warnings #disable 3
Cookbook: Sequences/API 3
data type 3
process 3
#Always 3
rounding 3
Mapping data types 3
encapsulation 3
UCIS 3
implication operator 3
Analysis fifo 3
bad handle or reference 3
covergroup coverpoint cross coverage foreach 3
RAL UVM REGISTER 3
non static method 3
constraint array.sum() 3
enumerated 3
Assignment inside generate block 3
#uvm #bind #set #environment #test 3
unexpected IDENTIFIER 3
UVM Register Built-in sequence 3
Skew 3
m_sequencer 3
#mdarray #constraint #foreachconstraint #arrayliteral 3
c 3
uvm_config_db uvm_resource_db 3
passive agent set_drain_time 3
fork join _none 3
Handshaking 3
PCIe Gen 5 2
Cookbook: Matlab/Integration 2
dynamic array memory allocation 2
uvm layered sequencers dynamic constraint 2
socket connection 2
uvm_reg_bit_bash 2
dependencies 2
if-else VS implication Constraint 2
Period 2
Lint 2
#UVM #modelsim 2
#systemverilog #clock #verilog 2
Nested class 2
DPI backdoor access 2
Cookbook: Registers/FunctionalCoverage 2
#UVM #Parameter #virtual_interface 2
verification concepts 2
FPGA 2
specman 2
DPI-C import with dynamic array as argument 2
QUESTA 10.3a 2
bit width 2
TLM2.0 2
#enum #import 2
scripts 2
Verification Methodology 2
array locator method 2
constraintdistribution 2
simulation 2
block level testcase 2
cast 2
coverage sequence 2
rand_mode dynamic array 2
Cookbook: Sequences/Generation 2
$signed 2
uvm components compilation 2
IMPDLL 2
Backdoor method 2
this and parent arguments 2
#Always/assign 2
function and task 2
uvm_sv_unit 2
interface binding 2
programming 2
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