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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Clock-Domain Crossing
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

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      • Coverage Forum

    • Additional Forums

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      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Emulation User Forum 2020 | Hyderabad
      • DVCon 2020 | San Jose, CA
      • User2User MARLUG - Laurel, MD
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • All On-Demand Seminars

    • Recording Archive

      • DAC 2019 Session Recordings
      • User2User Silicon Valley 2019
      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • All Recordings

    • Mentor Training Center

      • SystemVerilog Fundamentals
      • SystemVerilog UVM
      • SystemVerilog Randomization
      • Instructor-led Training

    • Mentor Learning Center

      • Introduction to Visualizer
      • Mastering Questa Learning Path
      • Stimulus Optimization with inFact
      • View all Learning Paths
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - December 2019
      • Verification Horizons - June 2019
      • Verification Horizons - February 2019
      • Issue Archive

    • About Us

      • Verification Academy Overview
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      • Contact Us

    • Training

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      • Questa® inFact
      • Functional Verification Library
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Tag List

  • #systemverilog 354
  • #uvm 187
  • uvm 142
  • UVM 124
  • assertion 87
  • System Verilog 83
  • SVA 77
  • Assertions 62
  • Assertion system verilog 56
  • RAL 51
  • systemverilog 47
  • constraint 45
  • #UVM #RAL 43
  • #SystemVerilog #FunctionalCoverage 41
  • uvm_config_db 36
  • DPI 34
  • constraint randomization 32
  • sequence 32
  • #systemverilog #Arrays 32
  • SystemVerilog 31
  • coverage 31
  • interface 30
  • scoreboard 26
  • #randomization 25
  • SVA Assertion 24
  • uvm_reg 24
  • ovm 24
  • class 24
  • constraints 24
  • functional coverage 23
  • uvm_sequence 22
  • assert property 22
  • cross coverage 21
  • randomization 20
  • Advanced UVM Register 20
  • system verilog assertion SVA 20
  • assertion systemverilog 20
  • SV 20
  • #coverage 19
  • virtual sequence 19
  • associative array 18
  • Dynamic Array 18
  • Package 18
  • queue 18
  • #systemverilog #ASSERTION 18
  • coverpoint 18
  • config_db 17
  • Inheritance 16
  • Learning System Verilog 16
  • virtual interface 16
  • bind 16
  • analysis port 15
  • mailbox 15
  • OOPS 15
  • Formal Verification 15
  • covergroup 15
  • Web Seminar 15
  • array randomization 15
  • Verification Horizons 15
  • Verilog 14
  • ASSERTION BASED VERIFICATION 14
  • driver 14
  • Constraint SystemVerilog 14
  • UVM phases 14
  • clock 13
  • Constraint random verification 13
  • Polymorphism 13
  • $cast 13
  • sequencer 13
  • #SVA 13
  • tlm 13
  • task 13
  • parameter 12
  • #queues 12
  • Seminar 12
  • constrained random generation 12
  • factory 12
  • system verilog assertion 12
  • array 12
  • fork join 12
  • p_sequencer 11
  • code coverage 11
  • UVM uvm_test 11
  • #systemverilog #Arrays #packedarrays #unpackedarrays 11
  • assert 11
  • randomization constraints 11
  • Bus interface 11
  • Portable Stimulus 11
  • BFM 11
  • questasim 11
  • virtual sequencer 11
  • systemc 11
  • uvm_info 11
  • Randomize 10
  • Cookbook: UVM 10
  • Coverage bins 10
  • casting 10
  • uvm register model 10
  • Clocking Block 10
  • Dave Rich 10
  • questa 10
  • VIP 10
  • event 10
  • VHDL 10
  • Verification 9
  • $display 9
  • uvm_tlm_analysis_fifo 9
  • property 9
  • event trigger 9
  • #uvm #verilog 9
  • configuration 9
  • modport 9
  • uvm_reg_block 9
  • uvm_reg_map 9
  • systemverilog datatypes 9
  • uvm ral 9
  • override 9
  • Cookbook: Phasing 9
  • Cookbook: Scoreboards 9
  • dist 9
  • wait statement 9
  • uvm_driver 9
  • dynamic arrays 9
  • uvm uvm_config_db 9
  • uvm_config_db #(...)::get() 9
  • Race condition 9
  • functions in system verilog 9
  • Event Regions 9
  • Systemverilog Assertion 9
  • multiple agents 9
  • fifo 9
  • configdb 8
  • macros 8
  • accessing the associative array elements 8
  • UVM_VERBOSITY 8
  • sequence and sequencer 8
  • Cookbook: Cookbook Code Examples 8
  • function 8
  • Parameters 8
  • checker 8
  • interface class 8
  • constraints systemverilog 8
  • introduction to system verilog 8
  • system verilog constraints 8
  • unpacked array 8
  • constraint array 8
  • field macros 8
  • uvm_error 8
  • class handle 8
  • enum 8
  • dpi-c 8
  • uvm_component 7
  • System Verilog Virtual Functions 7
  • #systemverilog #UVM 7
  • UVM Configuration database 7
  • Verification Academy Technology Series 7
  • Parameterized classes 7
  • static method 7
  • UVM monitor 7
  • argument pass by ref 7
  • sequences 7
  • TLM FIFO related 7
  • Constructor 7
  • reset 7
  • modelsim 7
  • Overridding parameterized class 7
  • typedef 7
  • uvm_object 7
  • concurrent assertion 7
  • UVM_PHASE 7
  • 2D array SystemVerilog 7
  • Checkers 7
  • program block 7
  • backdoor 7
  • Cookbook: Registers/ModelStructure 7
  • uvm virtual interface 7
  • formal verification assertion 7
  • Interfaces 7
  • generate 7
  • fork join in loop 7
  • Compilation Error 7
  • FATAL ERROR 7
  • SOC verification 7
  • agent 7
  • TLM ports 7
  • Use of virtual sequence and virtual sequencer. 7
  • uvm_sequence_item 7
  • comparator 7
  • actual interface 7
  • uvm_mem 7
  • timing checks 7
  • Verification IP 6
  • Debug 6
  • uvm_event 6
  • create() and new() 6
  • semaphore 6
  • uvm_analysis_imp 6
  • assertion coverage 6
  • Clock generator 6
  • Real datatypes 6
  • constraint dist 6
  • SystemC UVMConnect 6
  • UVM callback 6
  • #verilog 6
  • monitor 6
  • Transition Coverage. 6
  • Questa® Formal Verification Apps 6
  • #systemverilog #ASSERTION #bind 6
  • vcs 6
  • real numbers 6
  • static 6
  • Cookbook: Coverage/Testplan to Functional Coverage 6
  • import 6
  • coverage system verilog cover bins 6
  • error 6
  • UVM Sequence Library 6
  • system verilog testbench 6
  • uvm_reg_adapter 6
  • Arbitration 6
  • #interface 6
  • Cookbook: Registers 6
  • UVM phase methods 6
  • Assertions using Generate Block 6
  • Active UVM models 6
  • glitch 6
  • Queues 6
  • continuous assignment 6
  • set_type_override_by_type 6
  • SVA checkers 6
  • #error 6
  • run_phase 6
  • uvm register 6
  • registers 6
  • system verilog assertions 6
  • UVM Driver 6
  • for loop 6
  • RAL register UVM 6
  • generate block 6
  • deep copy 6
  • module 6
  • Delay 6
  • #sequence 6
  • function new 5
  • #configuration 5
  • generate macro `define 5
  • UVM MEMORY MODELING 5
  • run_phase() 5
  • Command Line Processing 5
  • always_comb 5
  • Mirrored values and desired values in UVM RAL 5
  • UVM Factory Registration 5
  • start_item 5
  • testbench 5
  • Polymorhphism 5
  • randc 5
  • new function 5
  • constraints for random variables 5
  • set_inst_override 5
  • #uvm #callback 5
  • cover groups 5
  • Extended Class 5
  • classes 5
  • File I/O 5
  • UVM_OBJECT and UVM_COMPONENT 5
  • sprint 5
  • unique 5
  • functional verification 5
  • Flow UVM 5
  • reference model 5
  • hierarchical reference 5
  • CDC 5
  • uvm_hdl_force 5
  • array interface parameterized 5
  • Systemverilog DPI 5
  • memory 5
  • constraint solver 5
  • Advanced Verification 5
  • uvm_warning 5
  • set_config_object 5
  • illegal bins 5
  • DUT 5
  • predict 5
  • $realtime 5
  • Constraining a random variable 5
  • Cookbook: Sequences/Slave 5
  • enumeration datatype 5
  • +uvm_set_severity 5
  • File reading 5
  • set_type_override 5
  • Resource_db 5
  • functions 5
  • fork join_any 5
  • uvc 5
  • initialization 5
  • uvm agent 5
  • uvm_monitor 5
  • driver monitor 5
  • build_phase 5
  • UVM_reg_field 5
  • constraint foreach loop 5
  • Methodology 5
  • error injection 5
  • #uvm #factory 5
  • Course 5
  • start() in sequencer 5
  • parameterized 5
  • clone() 5
  • sequencer and driver 5
  • Register abstraction Layer 5
  • fork join_none multiple threads 5
  • Cookbook: Registers/SequenceExamples 5
  • uvm_transaction 5
  • create macros or general functions 5
  • UVMConnect 5
  • phase objection 4
  • Queues in system verilog 4
  • return data 4
  • DUT parameters 4
  • uvm_do macros 4
  • systemverilog assertion concurrent 4
  • string 4
  • uvm_scoreboard 4
  • $monitor 4
  • pass by reference 4
  • Cookbook: Registers/StimulusAbstraction 4
  • inout 4
  • constraints array-constraints 4
  • frontdoor 4
  • environment 4
  • Xilinx 4
  • ignore_bins 4
  • first_match 4
  • raise_objection and drop_objection 4
  • uvm_reg frontdoor backdoor 4
  • implication operator 4
  • inherited_classes 4
  • register layer 4
  • wire 4
  • program 4
  • regressions 4
  • multiple interface 4
  • automatic variables 4
  • interface in system verilog 4
  • uvm_analysis_imp and uvm_analysis_export 4
  • uvm connect 4
  • Sequence Layering 4
  • UVM system verilog 4
  • for loop fork join_none 4
  • events 4
  • RAL UVM adapter 4
  • Connect_Phase 4
  • register adapter 4
  • end of test mechanism in UVM 4
  • UVM reuse 4
  • logic 4
  • sequence body() 4
  • config 4
  • cover property 4
  • reuse 4
  • gcc 4
  • forever loop/fork-join 4
  • define struct 4
  • Active Monitoring 4
  • cross 4
  • AHB 4
  • +uvm_set_inst_override 4
  • on the fly reset 4
  • Pipelined 4
  • cover property SVA 4
  • testbench environment 4
  • UVM TLM Analysis port 4
  • master and slave 4
  • uvm_reg_predictor 4
  • uvm_factory 4
  • uvm_sequencer 4
  • random stability 4
  • randomization error 4
  • assignment 4
  • chris_hue 4
  • SEED 4
  • Assertion binding 4
  • sequence control 4
  • AMBA AXI 4
  • uvm error 4
  • Low Power | UPF 4
  • System-verilog 4
  • array methods 4
  • Factory Overrides 4
  • compilation 4
  • Cookbook: Sequences/Stopping 4
  • DPI import 4
  • cross coverage bins 4
  • Multiple Sequences 4
  • SV DPI 4
  • packed array 4
  • tlm_fifo 4
  • LRM 4
  • HDL designer systemverilog interface 4
  • Callbacks 4
  • UPF + power aware 4
  • force signal 4
  • uvm_env 4
  • monitor to scoreboard 4
  • coverage transition bins 4
  • Infinite loop 4
  • initial_block 4
  • get set 4
  • structure and union 4
  • synthesize 4
  • timeout 4
  • I2C 4
  • timeunit 4
  • FSM 4
  • function coverage 4
  • bus2reg 4
  • System Verilog Verilog File Read Operation 4
  • Cookbook: Driver/Pipelined 4
  • transactions 4
  • uvm_report_server 4
  • Cookbook: Registers/BackdoorAccess 4
  • while 4
  • binding in SV 4
  • array of covergroups 4
  • array slicing 4
  • Null pointer dereference 4
  • assert(std::randomize(variable)) 4
  • uvm register w1c 3
  • UVM Configuration 3
  • unexpected IDENTIFIER 3
  • uvm_object_utils 3
  • mirrored value 3
  • raise objection 3
  • SVA Arbiter 3
  • shuffle 3
  • parameterized class 3
  • urandom 3
  • signed arithmetic 3
  • foreach 3
  • uvm overriding 3
  • Bind Factory UVM 3
  • uvm_field_int 3
  • virtual 3
  • fork-join_none 3
  • Bins 3
  • array of defines 3
  • $stable 3
  • #signal_force 3
  • UVM1.1d documentation source code 3
  • I2C protocol 3
  • Blocking 3
  • asynchronous 3
  • UVM Register Built-in sequence 3
  • get_response 3
  • interface connections 3
  • System verilog for loop 3
  • mid test reset test sequence 3
  • sv env 3
  • Function new() 3
  • uvm_printer 3
  • Modelling 3
  • analysis port; connection;connect_phase 3
  • verilog blocking assignments 3
  • begin_tr 3
  • SIGSEGV 3
  • $display hierarchy 3
  • simulation performance 3
  • Questa inFact 3
  • $past 3
  • thread 3
  • OVM Systemverilog 3
  • SCE-MI for Co-Emulation 3
  • compare 3
  • non static method 3
  • UVM raise and drop objection 3
  • multidimensional array systemverilog 3
  • Timescale issue 3
  • if condition 3
  • ASIC/IC Verification Trends 3
  • performance 3
  • #systemverilog DPI 3
  • assertion ##1 3
  • UVM Reporting 3
  • always_ff 3
  • raise_objection in pre_body() 3
  • shallow copy 3
  • Cookbook: Code Example Downloads 3
  • OOP 3
  • division 3
  • #APB 3
  • wait_modified() 3
  • Calling Sequence inside a sequence 3
  • behavioral model 3
  • Generating sequences 3
  • API to access Ral model in OVM 3
  • Abstract class 3
  • Mapping data types 3
  • SVA:$past 3
  • randc usage constraint 3
  • run_test(). 3
  • uvm_hdl_deposit 3
  • sequences and properties 3
  • array interface in uvm_config_db 3
  • UVM Predictor UVM_REG_MAP 3
  • Non-blocking 3
  • Cookbook: Sequences/LockGrab 3
  • enumerated 3
  • Write 3
  • agents 3
  • #systemverilog interface 3
  • #systemverilog#deepcopy 3
  • uvm_analysis_port 3
  • Assertion : How to handle when delay in the signal. 3
  • reporting 3
  • convert 3
  • shared object 3
  • Cookbook: Config/ConfiguringSequences 3
  • Harry Foster 3
  • Analog behavioral model 3
  • rounding 3
  • static property 3
  • $asserton 3
  • assertion synthesis checker SystemVerilog 3
  • uvm_sequence uvm_sequencer 3
  • syntax error 3
  • singleton class 3
  • systemVerilog Queue Scoreboard UVM 3
  • DPI error 3
  • get_next_item 3
  • class issue 3
  • ucdb 3
  • Cookbook: Testbench/Blocklevel 3
  • assert #0 3
  • SV constraint 3
  • #systemverilog#multidimentional arraya #memory 3
  • reading .txt file in UVM driver 3
  • AXI VIP 3
  • `uvm_do_with 3
  • assertion errors 3
  • c 3
  • implementation 3
  • parameterized interface 3
  • Transaction 3
  • UVM SystemVerilog 3
  • #delay uvm_components 3
  • fork 3
  • Abstract interface 3
  • $fell 3
  • EDA Playground 3
  • Cookbook: Questa/CompilingUVM 3
  • connect_phase in uvm 3
  • #packed array and queues 3
  • Multi-dimensional arrays 3
  • UVM 1.2 3
  • #reset 3
  • constraint for loop 3
  • randomize with 3
  • $time 3
  • create 3
  • class override 3
  • UCIS 3
  • AHB burst 3
  • SV Constraint Solver 3
  • uvm run_phase 3
  • disable fork 3
  • system verilog module 3
  • UVM Coverage 3
  • uvm_phases 3
  • uvm_cmdline_processor 3
  • pullup 3
  • verification plan 3
  • UPF 3
  • static variable 3
  • connect sequencer 3
  • hierarchical task call 3
  • UVM OBJECTIONS 3
  • uvm_reg_sequence 3
  • $fscanf 3
  • Synchronization 3
  • UVM RAL Backdoor Write hdl_path 3
  • get_config_object 3
  • type_id::create() 3
  • end_tr 3
  • Questa® Power Aware Simulator 3
  • assume 3
  • UVMC Compilation 3
  • UVM Reg model query 3
  • ifdef 3
  • local variables 3
  • tlm port 3
  • tasks 3
  • verbosity 3
  • finish_item 3
  • Cookbook: Agent 3
  • test 3
  • UVM sequence UVM hierachy 3
  • C++ 3
  • put_port 3
  • clocking block event 3
  • Streaming Operator 3
  • Assertion-Based Verification 3
  • predictor 3
  • fork join_any fork join_none 3
  • $root 3
  • passive agent 3
  • two clocks 3
  • Questasim 10.0b 3
  • delay timescale timeunit systemverilog 3
  • Skew 3
  • passive agent set_drain_time 3
  • Cookbook: Sequences/VirtualSequencer 3
  • Null Object Access 3
  • cross coverage bins constraints 3
  • memory verification 3
  • TLM 2.0 3
  • `define macro 3
  • grab regmodel sequencer 3
  • always blocks 3
  • multithreading 3
  • Cookbook: Analysis 3
  • realtime 3
  • signed 3
  • ports 3
  • waveform 3
  • main_phase 3
  • Parent to an object 3
  • questa formal 3
  • fork join join_none 3
  • Expression Coverage 3
  • uvm uvm_reg 3
  • SystemVerilog Constructs 3
  • time 3
  • Wilson Research Group Study 3
  • systemverilog mailbox 3
  • UVM Questa 3
  • Virtual methods 3
  • stuck between run_phase and extract_phase 3
  • factory overriding at run time 3
  • Cookbook: Sequences/Hierarchy 3
  • timeout value 3
  • derived class 3
  • automatic 3
  • task argument 3
  • repetition 2
  • vcoVER MERGE 2
  • BURST 2
  • sv dpi export 2
  • axi amba protocol 2
  • Copy() 2
  • uvm scoreboard methodology 2
  • vsim 2
  • grab ungrab stop_sequences 2
  • disable_fork 2
  • SV systemVerilog constraints array 2
  • #uvm #parameter #uvm_subscriber 2
  • push_pull 2
  • wait for change 2
  • m_uvm_get_type_name_func 2
  • 2-dimensional dynamic array randomization 2
  • starting_phase in uvm 2
  • backward compatible 2
  • uvm_config_db uvm_resource_db 2
  • Implication in cover property 2
  • Test-plan 2
  • poke_field_by_name 2
  • clocking block sequence coverage 2
  • ncelab: *E 2
  • uvm_reg_bit_bash_seq 2
  • event scheduling 2
  • Cookbook: Driver/Sequence API 2
  • imported c function 2
  • hierarchical constraints 2
  • Systemveilog 2
  • deep copy and shallow copy 2
  • override parameterized 2
  • argument 2
  • Accellera Portable Stimulus Standard 2
  • random 2
  • Assertions $stable 2
  • sequencers 2
  • this. 2
  • $rose 2
  • Covergroup instance for an array 2
  • sequence_library 2
  • virtual polymorphism 2
  • multi-threading 2
  • factory registration 2
  • bit slice in force syntax 2
  • do_print 2
  • within 2
  • get_field_by_name 2
  • address range 2
  • $value$plusargs 2
  • learning 2
  • enum different data types 2
  • Timing checks using $skew 2
  • UVMF 2
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