Other Tags

OVM x 2495
SystemVerilog x 7332
Announcements x 155
UVM x 7138
Downloads x 97
registers x 9
verbosity x 4
reuse x 4
interface-connections x 3
qvp x 1
i2c-testbench x 2
erm x 1
uvm-connect x 7
tlm x 19
Coverage x 615
configurable-bfm x 2
test-messages x 1
testbench-environment x 4
semaphore x 14
assertion x 510
gcc x 2
uvm-code x 2
socket-connection x 2
function x 9
convert x 4
uvm_error x 12
uvm_info x 20
uvm_warning x 7
set_config_object x 5
systemc x 11
scoreboard x 37
ahb2apb-protocol x 2
cover-groups x 5
coverpoint x 32
testbench x 18
config_obj x 1
error x 21
sequences x 8
sequencer x 26
Monitor-can-drive-interface-level-signals x 1
Python-Script x 4
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raise_objection-in-pre_body x 3
uvm_sequence_item x 11
uvm_transaction x 5
defaultbins x 1
illegal_bins x 2
systemverilog-bins x 1
SV-simple-class-creating-issue x 1
sV-DPI-cpp-fatal-error x 2
wait_modified x 3
RAL x 106
Warning-vsim-3764 x 1
parameterized x 5
parameterized-sequencer x 1
p_sequencer x 15
simulation-Terminate x 3
reg x 1
wire x 7
logic x 18
System-Verilog x 241
PLI-SystemC x 1
systemVerilog-Queue-Scoreboard-UVM x 3
on-the-fly-reset x 4
Flow-UVM x 5
cross x 8
automatically-generated x 2
PSL x 2
UVM_FATAL--0-reporter-BUILDERR x 2
uvm-error x 9
delay-adding-in-sub-phase x 1
randomization-constraints x 10
VHDL-UVM-RECORDS-EXAMPLE x 2
processor-uvm x 1
Regarding-memory-allocation-of-an-object-in-SV x 2
How-to-split-and-merge-the-transactions-in-AXI-protocol x 1
Write x 4
uvm_analysis_imp x 7
configuration x 21
modport x 12
bind x 29
coverage-transition-bins x 6
Cookbook-Registers x 9
UVM-RNDFLD-Randomization x 1
bounded-objects x 1
mailbox x 16
transactions x 4
configure-multiple-slaves x 1
VPI-force-halt x 1
class x 38
ocp x 2
uvc x 9
uvm-uvm_config_db x 25
array-interface-parameterized x 5
uvm_config_db x 57
conditional x 3
generate x 12
hierarchical x 2
reference x 1
DUT x 6
associative-array-inline-constraint x 2
override x 17
uvm-events-synchronisation x 3
class-issue x 3
Clock-gating-check x 2
program-block x 9
multithreading x 3
multi-core x 1
uvm-register x 6
Race-condition x 18
mailbox-in-sv-is-not-serving-after-some-delay x 1
Package x 30
MATLAB-generated-C-functions-use-in-UVM x 1
UVM-Subscriber-write-method-error x 1
questasim x 14
sequence-killed-or-finished x 2
Streaming-Operator x 9
display x 12
truly-parallel-sequences x 1
Override-type-uvm_reg x 1
virtual-interface x 21
questa x 11
default_sequence x 5
virtual-sequencer x 13
Cookbook-Configuration x 2
TPRGED x 1
UVM_TESTNAME x 2
multiple x 3
randsequence x 2
functional-coverage x 25
hierarchy x 8
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interface-macro-define x 1
virtual-sequence x 20
register-model-volatile x 2
parameter x 22
typedef x 12
BURST-Transfer-AHB x 2
grab-regmodel-sequencer x 3
UVM_VERBOSITY x 12
SEED x 6
PRNG x 2
import x 7
include x 5
ovm-uvm x 2
Sequential-sequence x 2
cross-coverage x 31
autobins x 2
System-Verilog-IP x 1
Polymorphism x 20
Method-Overriding x 3
Cookbook-Cookbook-Code-Examples x 8
shallow-copy x 4
deep-copy x 7
Delay-between-Phases x 1
UVM-Sequence-Library x 7
Vmm-channel x 2
uvm-agent x 7
tlm-port x 3
SVA x 264
Half-Clock-Check x 2
override-parameterized x 2
Driver-Class-Generator-Class x 2
uvm_reg_adapter x 7
UVM-Register-Built-in-sequence x 3
adapterget_item x 1
uvm-cookbook-registers-guide x 1
configure-monitor-random-items x 2
virtual-forever-sequence-wait_for_signal x 1
RUVM x 2
Block-Instance x 1
sequence x 83
sequencer-agents x 2
Constraint-SystemVerilog x 14
tlp x 1
UVM-phase-methods x 6
error-injection x 6
OVM-Systemverilog x 3
root-access-from-within-packages-is-not-allowed x 2
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FATAL-ERROR x 12
SDRAM x 1
interface x 80
config_db x 21
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analysis-port x 21
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structure-and-union x 7
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constraint x 70
re-programming x 1
DPI-error x 6
Questasim-100b x 2
run-error x 2
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ovm-interface x 1
adc-model x 1
contribution x 1
guide x 1
tutorial x 1
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reporting x 3
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testflow x 1
UVM-Coverage x 11
Reg-block x 1
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Early-Phase-End x 1
UVM_PHASE x 12
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Clock-generation-block-inside-Program-block-in-SV x 1
UVM-MEMORY-MODELING x 6
SV x 32
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Arbitration x 7
Priority x 4
inout x 5
uvm_driver x 11
inconsistent x 1
net-object x 1
predict x 6
Cookbook-CBasedStimulus x 2
uvm_reg-frontdoor-backdoor x 5
Randomize x 12
UVM-raise-and-drop-objection x 3
Infinite-loop x 4
pre_reset_phase x 1
unknown x 1
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TLM-connection-topology x 2
UVM-put-into-OVM x 1
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Clock-generator x 6
full-access x 1
Recording x 2
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debug_connected_to x 1
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task x 22
return-data x 4
AHB-burst x 7
uvm_do-sequences-randomization x 1
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compilation x 6
multi-threading x 3
driver-model x 1
reference-model x 10
questasim-102C x 2
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waveform x 4
DPI x 42
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raise-objection x 3
drop-objection x 2
functional-verification x 5
online-course x 2
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layer-sequence x 1
RAL-register-UVM x 9
sequencer-and-driver x 5
macros x 14
checker x 15
iff x 2
rose x 5
fell x 6
posedge x 1
posedge-clk x 3
posedge-clk-begin x 3
systemverilog-coverage-cross x 3
dynamic-arrays x 11
Cookbook-TestbenchBlocklevel x 2
hierarchy-reference x 3
multi x 1
dimensional x 1
associative x 3
No-they-are-not-mutually-exclusive x 1
From-your-comment x 1
I-understand-that-it-is-possible-to-cross-transition-coverage-with-other-coverage x 1
Coverage-Back-Annotation x 1
How-to-send-data-to-the-DUT x 1
if-statement-in-constraint x 1
concatenation x 4
Maximum-size-of-Queue-in-System-Verilog x 1
packing-in-umv x 1
system-verilog-queue-operation x 1
late-randomization x 2
get_response x 10
seq_item_portput-rsp x 1
Dropping-response x 1
Response-API x 2
use_response_handler x 1
uvm_event x 10
multiple-agent x 1
uvm_event_pool x 5
trigger x 1
event-trigger x 9
assert x 13
Inout-port x 4
reading-txt-file-in-UVM-driver x 3
SCE-MI-for-Co-Emulation x 3
ovm_comparer x 2
complement x 1
negative x 1
signed x 9
Cookbook-CoverageUART-Example-Covergroups x 2
OOPS x 19
Cookbook-RegistersBackdoorAccess x 5
broadcast-writes x 3
aliased-registers x 2
layered-sequence x 3
FSM x 9
UVM-monitor x 19
deep-copy-and-shallow-copy x 5
RAL-model-in-OVM x 1
type-constructor-class x 1
constraint-randomization x 220
preprocessor-directives x 1
directed-test x 1
LRM x 8
RAL-UVM-adapter x 4
casting x 18
tlm_fifo x 4
base-class x 4
derived-class x 3
Memory-Model-Verification x 1
get_coverage-constant-RAM-verification-UVM x 2
multiple-interface x 4
uvm_object x 12
set_inst_override x 5
set_type_override x 8
verilog-model x 1
randomize-with x 5
Cookbook-SequencesStopping x 4
local-variables x 3
vcoVER-MERGE x 2
sv-dpi-export x 3
OVM-Register-model x 2
API-to-access-Ral-model-in-OVM x 3
9bit-bytes-for-pack_bytes-function x 1
end-of-test-mechanism-in-UVM x 4
uart-download x 1
SystemVerilog-Constructs x 3
uvm_field_array_int x 1
Register-abstraction-Layer x 5
sequence-control x 4
assertstdrandomizevariable x 5
queue x 21
monitor x 25
Cookbook-MatlabIntegration x 2
confiburation-factory-visibility x 2
get_config_object x 3
macro-nested x 2
timescale-SystemVerilog-vmm x 2
bOVM_REGISTER_DRIVER x 1
OVM_REGISTER_SEQUENCER x 1
OVM_REGISTER_MONITOR x 1
OVM_REGISTER_DRIVER x 1
Profiling x 1
dpi-c x 19
imported-c-function x 2
Questa-debugger x 1
macro-define-comment-white-space x 1
system-verilog-analogue-port-real-types x 2
frequency x 2
uvm_report_server x 6
get_report_verbosity_level x 1
UVM-sequence-UVM-hierachy x 3
Sequence-Layering x 4
Multiple-Sequences x 4
create x 8
build_phase x 10
Address x 2
SV-DPI x 4
Cookbook-SequencesSlave x 6
clocking-block-sequence-coverage x 2
UVM-11d-uvmsvh x 1
comparator x 8
set_covergroup_expression x 1
systemverilog-local-variables-assertion x 2
UVM-Questa x 3
uvm_in_order_comparator x 1
difference-between-uvm_top--uvm_root x 1
turn-off-constraint x 1
Cookbook-RegistersSequenceExamples x 6
Multiple-requests x 3
Clock-range x 1
monitor-to-sequence-connection x 1
vhdl-record-struct-mapping x 1
uvm_sequence_lib x 1
Segmentation-fault x 1
connect_phase-before-build_phase x 1
static-variable x 3
read-string-array-from-file x 1
saving-coverage-data-on-demand x 1
Golden-Reference-Model x 4
GP-UVM x 1
generic-payload-UVM x 1
Mirrored-values-and-desired-values-in-UVM-RAL x 6
uvm-register-model-ofr-multiple-byte-register-in-soc x 2
ncelab-E x 2
CUVUNF-homedataSTB03cana0mainworkathakardebugdesignblkchiptbteststx_manuel_flow_controlsv x 1
7454-Hierarchical-name-component-lookup-failed-at-uvm_test_top-irun-E x 1
ELBERR-Error-during-elaboration-status-1 x 2
exiting-make--INCA_libs_usb20elabdone-Error-1 x 1
Hierarchical-name-component-lookup-failed-at-uvm_test_top x 1
functions x 6
get-set x 4
return-type x 1
class-variables x 2
VHDL x 13
Svinterface x 1
assertion-errors x 4
driver x 34
object-to-all x 1
object-to-one x 1
mid-test-reset-test-sequence x 3
UVM-Factory-Registration x 5
UVM_OBJECT-and-UVM_COMPONENT x 5
Create-and-new-function x 1
UVM-Golden-model x 1
reading-from-file x 1
HDL-designer-systemverilog-interface x 5
systemverilog-sequence x 1
array-unpacked-streaming-cast x 2
uvm_heartbeat x 2
Virtual-methods x 6
Bins x 6
uvm_analysis_imp-and-uvm_analysis_export x 5
TLM-ports x 7
delay-uvm_components x 8
vopt x 3
generic x 2
uvm_mem x 14
parameterized-macro x 2
fork-join-in-loop x 9
UVM-system-verilog x 6
SOC x 4
VIP-integration x 4
generate-macro-define x 7
is_active x 2
activepassive-agent-configuration x 4
interface-override x 1
Cookbook-Agent x 3
Cookbook-Scoreboards x 11
UVM-Driver x 15
Non-blocking x 5
Blocking x 3
factory x 18
uvm_sequence x 35
using-arrays-for-configuring-variables x 1
color x 1
stdout x 1
simulation-log x 1
uvm_hdl_force x 6
uvm_hdl_check_path x 2
backdoor x 10
AXI3 x 2
Read-Strobes x 1
define-macro x 3
real-numbers x 6
build-phase-in-run-phase x 1
shortreal x 1
multiple-agents x 10
configuration-object-scope x 1
property x 15
range x 1
Verification x 11
Advantages x 1
SV-constraint x 3
unique-values-in-two-arrays x 1
Arbiter-priority x 1
register-assistant x 2
automatically-simulator x 1
Cookbook-QuestaCompilingUVM x 3
verilog-blocking-assignments x 3
constructing-or-bulding-uvm-component x 1
umv-compare x 1
uvm_field_int x 3
Copy x 6
clone x 10
ignore_bins x 8
mux_2-using-sv x 1
set_type_override_by_type x 11
soft x 1
system-verilog-testbench x 6
sv-env x 3
Command-Line-Processing x 9
pass-by-reference x 4
UVM-TLM-Analysis-port x 8
put-port x 2
get-port x 1
System-verilog-for-loop x 4
Multi-dimensional-arrays x 4
timeunit x 4
dump-file x 1
transaction-debug x 1
Driver-and-Monitor-in-system-verilog x 2
stimulus-in-system-verilog x 2
programming-block x 1
interface-in-system-verilog x 4
OVM-SV-to-System-C-connectivity-using-TLM2 x 1
uvm-uvm_do_with-fork-join x 1
clock-generator-using-classes x 2
Read-Method x 1
UVM-Reporting x 7
setting-time-period-programmably x 1
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time-unit-declaration x 1
Package-interdependecy x 2
how-to-include-interface-into-a-package x 1
Access-Verilog-Array-in-Uvm-classs x 2
UVM-scoreboard-problem x 2
ctags-vim x 1
register-layer x 4
master-and-slave x 4
questa-formal x 3
UVM-uvm_test x 11
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connect-library x 1
Null-pointer-dereference x 6
PCIe x 3
Covergroup-instance-for-an-array x 2
directory-structure x 1
Cookbook-EndOfTest x 1
layering x 2
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Wrapper x 2
learning x 2
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uvm-overriding x 3
UVM-uvm-MEMORY-MODELING x 1
UVMRSRCNOREGEX x 2
suppress-uvm_warnings x 1
Assertion-binding x 5
attempting-to-start-a-null-item-from-sequence x 1
start_item x 7
uvm_do_with x 7
Overridding-parameterized-class x 7
grab x 2
ungrab x 2
interfaces-clocking-blocks-ports x 2
IMPDLL x 2
Parent-to-an-object x 3
ignore-sampled-coverage-conditionaly-later x 2
reactive-sequence x 4
error-in-class-extension-specification x 4
events x 5
UVM-RAL-Backdoor-Write-hdl_path x 3
OOP x 5
Composition x 1
Inheritance x 31
USB x 1
Cookbook-ConnectTwoKingdomsFactory x 1
local-function x 1
Disable-uvm-componentobject-utils-automation-message x 1
uvm_mem-frontdoor x 1
Parameter-overriding x 3
complier-directives x 1
fifo x 14
deterministic x 1
accessing-class-variables-in-a-loop x 4
SVA-Assertion x 42
Cookbook-RegistersStimulusAbstraction x 4
replace-field-value-in-rand-seq x 1
number-of-1s x 1
no-of-1s x 1
number-of-setbits-in-a-variable x 1
taskfunction-access-via-modport x 1
Verilog x 42
vcover-merge-master x 1
sequence-start-method x 2
introduction-to-system-verilog x 8
this-OOP-cast-stream x 1
Cookbook-ConfigConfiguringSequences x 3
UVM_CREATE-UVM_SEQUENCE x 2
array-of-boolean-values x 1
uvm_printer x 3
uvm_printer_row_info x 1
array-bins x 4
Cookbook-RegistersBuiltInSequences x 2
singleton-class x 3
fork-join_any-fork-join_none x 3
finish_item x 4
uvm_do-macros x 6
svBitVec-Size-Limit x 1
accept_tr x 2
begin_tr x 3
end_tr x 2
uvm_reg_map x 12
randomization x 109
enablingdisabling-coverage-in-config-class x 1
mixed-UVM-OVM x 4
VIP x 14
agents x 4
busses x 1
industry-standard x 2
stopping-due-to-build-errors x 1
get_severity_count x 1
set_severity_count x 1
Cookbook-UVM12Summary x 1
test_name-uvm x 1
parameter-override-class x 1
TB-architecture x 1
clocking-block-event x 3
unique x 8
Compile-UVM-12-in-Windos-64-bit x 2
command-not-found x 1
error-127 x 1
sequence-body x 7
UVM_MACROS x 1
datapath x 2
uvm_tlm_fifoflush x 1
uvm_in_order_class_comparator x 1
parameter-override-package-class x 1
Queues x 31
struct-in-queues x 1
bind-multiple-driver-replace-stubout-dut x 1
watchdog x 2
uvm_reg x 40
finish-from-uvm_root x 1
Sequencer-unlock x 2
UVM-QVIP x 1
register-mdel x 1
uvm_reg_bit_bash x 3
set_randstate x 1
Burst-access-using-RAL x 2
sverilog-vcs-systemverilog x 1
waiting-in-testclass x 1
sequencers x 2
commonrun-object x 1
Cookbook-StimulusSignal-Wait x 1
Missing-Code x 1
delay-timescale-timeunit-systemverilog x 4
reg-wire-logic x 1
Cookbook-Analysis x 3
Sequence-driving x 1
Cookbook-UVMEmulationExample x 1
How-to-override-base-classes-during-compile-time- x 1
topology x 2
pseudo-map x 1
reg2bus x 2
bus2reg x 4
generate-block x 9
hierarchical-reference x 5
genvar x 4
gcc-44 x 1
Questa-102c x 2
DUT-connection-using-wrapper x 1
transaction-override x 1
apply_config_settings x 1
static-method x 8
UVM-library-update x 1
guidelines x 2
Cookbook-ResourcesConfig-DB x 2
Cookbook-DriverSequence-API x 3
chained-implications x 2
vrslvdeclc3514 x 1
Clocking-Block x 19
Skew x 3
Delay x 7
Constraining-a-random-variable x 5
merging-functional-coverage-problem x 1
ESL x 1
RTL x 9
Methodology x 5
randc x 10
UVM-bind x 1
m_req_fifo x 1
FEC x 2
sequence-cannot-start x 1
posibility x 1
VRM x 2
usage-of-parameters-in-functions x 1
ovm_pkg x 1
import-ovm_pkg x 1
package-could-not-be-bound x 2
sysyem-verilog x 4
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phase x 3
uvm_monitor x 5
semaphore-keys x 7
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synthesize x 4
sequence-items x 1
Zero-Delay-Simulation x 1
Delta-Delay-Simulation-and-Unit-Delay-Simulation x 3
matlab x 3
Cross-coverage-in-UVM-Register-Layer x 1
SV-bind x 1
design-pattern x 1
decorator x 1
class-handle x 11
typed-constructor-call x 1
interface-classes x 1
system-verlog x 1
uvm-hierarchy x 1
binding-in-SV x 4
UVM_SUBSCRIBER x 2
Riviera-PRO-EDU-201410 x 1
printer-knobs x 1
sprint x 5
Branch-Coverage x 2
Expression-Coverage x 3
Focused-Expression-Coverage x 1
Modelsim-101d x 1
EDA-Playground x 4
ip-xact x 2
setting-default-sequence-in-tests x 2
starting_phase-in-uvm x 2
caption x 1
stuck-between-run_phase-and-extract_phase x 3
argument-pass-by-ref x 8
config_db-DUT x 1
uvm_packer x 3
simulation-profile x 2
Invalid-X-or-Z-in-state-expression-value-for-constraint x 1
unable-to-locate-hdl-path x 1
Parity x 1
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random-time-delay x 1
regressions x 4
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enumerated x 3
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Efficient-way-to-cross-transition-cover-points x 2
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slave-pipelined-sequence-driver x 1
uvm-best-practices-and-make-does-not-work x 1
system-verilog-assertion x 14
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array-slicing x 5
Assertion-How-to-handle-when-delay-in-the-signal x 5
module x 10
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uvm-matlab x 1
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type-operator x 2
vcs x 5
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I2C-protocol x 5
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GLS x 4
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N2 x 1
N4 x 1
N6 x 1
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code-coverage x 12
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dist x 11
item_done x 4
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VCD x 3
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tcl x 2
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cov_even x 1
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concurrent-assertion x 11
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modelsim x 7
Altera x 2
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vseq x 1
vseqr x 1
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makefile x 2
Parameters x 9
functions-in-system-verilog x 10
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fscanf x 4
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unix x 1
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subscriber x 1
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peek x 2
UVM11d-documentation-source-code x 3
defines-parameters-enumerate-types x 2
sequence-item x 10
struct-scoreborad x 1
Active-UVM-models x 6
merge-ucdbs-of-same-test-record x 1
SVA-bind x 2
Abstract-interface x 3
illegal-bins x 6
UVM_reg_field x 8
QUESTA-TRANS_AP x 1
QUESTA-AGENT-ANALYSIS-PORT x 1
TLM-20 x 4
uvm-macros x 1
objections x 2
system-verilog-assertions x 7
static x 8
initialization x 6
object x 3
uvm-register-w1c x 4
stable x 9
run_test x 6
inline-constraints-handling x 4
protocol-checks-using-assertions x 2
coverage-UVM x 2
tlm2 x 1
tlm1 x 1
Cookbook-Phasing x 10
uvm-simulation x 2
eclipse x 1
IDE x 1
plugin x 1
seq_type_override_by_type x 1
supernew x 2
Introducing-Delay-in-the-assertion x 1
BFM-interface-tasks-sequence x 2
Cookbook-SequencesVirtualSequencer x 6
always x 6
automatic x 4
Cookbook-CoverageTestplan-to-Functional-Coverage x 6
Clock-latch x 1
top-module-uvm x 1
Calling-Sequence-inside-a-sequence x 4
DFT x 2
constraints-systemverilog x 10
why-driver-display-statemnet-not-print-first x 1
sequencer-test-uvm x 1
Call-back x 2
sequence-and-sequencer x 8
tasks x 4
TLM-FIFO-related x 7
coverage-FSM-extraction x 1
const x 2
event x 16
uvm_macrossvh x 3
uvm_reg_hw_reset_seq x 3
uvm_default_report_server x 1
custom_report_server x 2
report-summary x 1
Formal-Verification x 25
Seminar x 12
Formal-Apps x 2
questa-error x 1
thread x 5
asyncronous-reset x 2
behavioral-model x 3
interface-block x 1
clocking x 1
compare-different-member-of-two-scoreboard-queues x 1
program x 4
sequence-items-unnecessarily-randomized x 1
uvm_sv_unit x 2
uvm-harness x 2
cover x 1
Checkers x 11
force-signal x 13
sequences-randomization x 1
Verification-Academy-Technology-Series x 7
Questa-Connectivity-Check x 1
WDT-UVM-Verificaiton x 1
Bind-Interface-failed x 2
solution x 1
UVM-clock-period-configuration x 2
program-and-module-differences x 2
Cookbook-ReportingVerbosity x 3
Override-report-severity x 1
cast x 28
questasim-error x 3
Verilog-Task-Sequences x 1
Questa-inFact x 5
Frocing-the-DUT-signal x 2
system-verilog-package-compilation x 2
modelsim-altera-starter-edition x 2
vsim x 3
UVM-phases x 18
run_phase x 19
timeout-value x 3
UVM_VERBOSITY-virtual-sequences x 1
architecture x 3
predictor x 4
system-verilog-resolution-function x 1
Transaction-Streaming x 1
Example x 1
Transaction-relations x 1
monitor-use x 1
nettype x 1
UVM-copy-derived-base-extend-cast x 1
UVM-reuse x 4
Maximum-characters-in-a-single-line x 1
coding-guidelines x 2
instance-name x 2
factorycreate x 2
Clock-domain-crossing x 3
CDC x 6
systemverilog-class-parameterized-static x 1
Subscribers x 1
monitors x 1
assigning-class-instances x 2
different-libraries x 1
illegal-class-assignment x 2
unbounded-delay-range x 1
grab-ungrab-stop_sequences x 2
SVA-sequence x 4
uvm_macro x 2
no-access x 1
asynchronous x 10
reset x 17
Visualizer-Debug-Environment x 2
register-out-of-bounds-address-location x 1
Env-diagram-in-uvm x 1
driver-monitor x 6
systemverilog-scheduling x 2
events-region x 2
determenism x 1
Downtime x 1
verification-plan x 4
test-plan x 3
coverage-model x 1
Cookbook-EmulationExample x 1
timescale-package-class x 1
instantiation-vs-inheritance x 3
parameterized-interface x 4
class-override x 4
Simulator-Race-Multiple-Clock-Domain x 1
uvm_reg_predictor x 4
has_do_available x 1
ovm-factory-constraint_mode x 1
wait-statement x 14
Interrupt-service-routine x 2
final-phase x 2
associative-array x 30
SystemC-RTL-UVM x 1
Questa-104 x 1
Assertion-viceversa x 1
UVM-Configuration-database x 12
nested-suffix-implication x 1
sequences-and-properties x 3
enum x 24
covergroup-coverpoint-cross-coverage-foreach x 3
function-new x 11
function-build x 1
Systme-verilog-Constraints x 2
Cookbook-RegistersAdapterContext x 2
combine-assertion x 1
mirror x 3
Code-Coverage-waivers x 2
RTL-coverage x 3
Questa-Verification-Management x 1
strong-typing-rules x 2
enumeration-datatype x 6
Real-variable-comparison x 1
comparison x 1
realtime x 10
UVMConnect x 6
UVMC x 3
callbacks-vs-factory-overriding x 1
UVM-verification-steps x 2
glitch x 8
clock x 24
Event-Regions x 10
systemverilog-continue-fork x 1
define-struct x 4
m_uvm_get_type_name_func x 2
uvm-virtual-interface x 9
uvm_object_utils x 5
erroruvm_object_utils-is-undefined x 1
error-uvm_config_db-is-undefined-variable x 1
extending-uvc x 1
higher-level-protocol x 1
do_not_randomize x 2
sequence-randomization x 2
uvm-randomization x 2
randomization-error x 4
illegal-contraints x 1
systemverilog-parameter x 1
Questa-Power-Aware-Simulator x 3
syntax x 3
recovery x 1
time-unit x 1
system-task x 4
vsim-3996 x 1
vsim-3978 x 1
vsim-3567 x 1
start-in-sequencer x 5
sytem-verilog x 2
print x 3
timing-violation-enabledisable x 2
array-interface-in-uvm_config_db x 3
assertion-1 x 4
internal-signal-in-DUT x 4
transaction-verbosity x 1
assertion-synthesis-checker-SystemVerilog x 3
same-function x 1
timeout x 6
Nonvirtual-methods x 1
uvm-layered-sequencers-dynamic-constraint x 2
NPITEM x 1
Compilation-Error x 8
interface-binding x 2
sequence-scoreboard-syncronization x 1
ral-backdoor x 3
systemverilog-assertion-concurrent x 4
get_next_item-handshaking-uvm x 3
formal-verification-assertion x 9
Questa-Formal-Verification-Apps x 8
display-hierarchy x 3
field-macros x 9
print-transaction x 2
syntax_error x 2
edaplayground x 3
uvm-uvm_object-uvm_transaction x 1
uvm_do_on x 3
accessing-the-associative-array-elements x 11
system-verilog-constraints x 16
Question x 1
UVM_INFO-component-name-meaningless x 3
root x 3
Independent-hierarchy-access x 2
uvm-ral x 88
RAL-register-functional-coverage x 1
uvm-run_phase x 3
query x 1
FileReading-FileIO x 2
Questasim-for-VHDL x 2
Cookbook-UVM x 14
UVM-monitor-scoreboard-sync-issue x 2
Cookbook-RegistersQuirkyRegisters x 1
command-line-options x 1
Macro-class-definition x 1
runtime-speed x 1
uvm_sequence_base x 2
main_phase x 4
RAL-concept x 1
halting-a-sequencer x 1
testbench-export x 1
monitor-to-testbench-tlm x 1
Feeding-sequence-to-multiple-agent x 2
configdb x 8
assert-0 x 2
unexpected-IDENTIFIER x 4
Migration x 1
past x 8
severity x 1
Debug x 11
Portable-Stimulus x 11
uvm-push x 1
Lint x 2
Driver-sequencer-Handshake x 4
protocol-check-using-assertions-in-Interface x 1
Cookbook-MacroCostBenefit x 1
bad-handle-or-reference x 3
BNF-1800-2012 x 1
stop-sequencer x 1
testbenching x 1
Transition-Coverage x 6
intelligent-scoreboard x 2
Virtual-Sequence-and-Virtual-Sequencer-advantages x 1
Coverage-Covergroups-Array-Embedded-Covergroup x 1
seq_item_port x 2
two-interfaces x 2
DPI-backdoor-access x 2
force-vcs-log x 1
NOA x 3
physical-interface x 1
UCIS x 3
Error-Cases x 2
image-link-is-also-there x 1
systemverilog-datatypes x 10
uvm-print x 3
file-logging x 1
SVApast x 3
Systemveilog x 1
uvm_registry x 2
export-DPI-C x 3
passing-arguments-by-reference-to-task x 2
data-flow-synchronization x 5
reg2bus-exicutes-much-earlier-than-monitor-sees-transaction-on-bus x 1
parameterized-class x 8
put_port x 3
soft-constraints-hard-constraints-constraints x 3
ovm_register_agent x 1
uvm-interface x 5
type-of-formal x 1
UPF--power-aware x 6
coverage-sequence x 2
item x 3
array-randomization x 18
uvm-uvm_reg x 5
assertion-nexttime- x 1
SVA-Transition-from-x--01 x 1
set_config_int_db x 1
get_config_int_db x 1
PNG-SUPPORT-DUMP-IMAGE x 1
simple-examples x 2
Xilinx x 3
running-multiple-testcases-in-sv x 2
Generic-clock-generation x 2
abstract-driver x 2
abstract-monitor x 2
SVA-Transition-coding-sequence-and-filter x 1
constraint-solver x 7
randomization-timeout x 1
SVA-Assertion-checking-for-multiple-signals-samipling-on-different-of-clocks x 1
class-parameter-overrides x 2
Out-of-file-SV-tasks x 1
Cookbook-OVMPhasing x 3
sequence-sum x 1
intermediate-sequencer x 1
testbench-porting x 1
uvm_field_array_-macro x 2
macro-for-realtime x 1
wire-delay-specify x 1
REQ x 4
RSP x 1
Pipelined x 4
slow x 2
covergroup x 32
signal x 2
virtual x 9
UVM-12 x 5
Simulation-and-Emulation x 1
prediction-monitor-scoreboard x 4
Duty-cycle x 2
Callbacks x 5
Rank x 1
vcover-ranktest x 1
wire-logic x 3
Cookbook-SequencesLockGrab x 5
asertion x 2
repetition x 2
APB3 x 1
Cookbook-SequencesHierarchy x 4
interface-class x 8
uvm_config_db-sequence x 1
Two-Drivers-for-same-protocol x 1
warning x 1
static-method-vs-method-with-static-lifetime x 1
mirrored-value x 4
Interface-Instantiation x 2
supress x 1
automatic-variables x 7
for-loop x 16
Interfaces-set-config-db-issue-for-multiple-interfaces-instance-of-same-agent x 1
process x 3
CRC5 x 2
assigning-and-retrieving-obj-from-the-dynamic-array x 1
get_end_time x 1
implication--operator x 1
for-loop-fork-join_none x 12
ordering-random-variable x 1
plusargs x 1
testplusargs x 2
UVM-sine-wave x 3
UVM-ports x 2
layered-agent-uvm_analysis_port x 1
uvm_set_severity x 5
attributes x 2
uvm_report_catcher x 2
cross-of-cross x 1
uvm-analysis-implementation x 2
add_reg x 1
uvm_reg_sequence x 4
unisim x 1
ddr x 1
array-of-covergroups x 6
timing-checks x 8
subcycle x 1
setup x 1
Course x 5
Neil-Johnson x 1
SVUnit x 2
UVM-starting_phasePH_TIMEOUT x 2
Verification-Horizons x 14
expression-coverage-generate-loop x 1
fork-join_none-multiple-threads x 8
Parameterized-classes x 8
binding x 2
Assertion-for-toggle-coverage x 1
File-reading x 7
uvm_factory x 7
Jenkins x 1
Abstract-class x 5
Nested-class x 2
uvm-output-monitor x 1
combinatorial-interface x 1
Cyclic-class x 1
Johnson-counter x 1
uvm_pool x 2
connect-sequencer x 4
Advanced-UVM-Register x 20
uvm-verilog-testbench x 1
BFM x 15
Use-of-virtual-sequence-and-virtual-sequencer x 10
get_event_pool x 2
dependencies x 2
dumpvars x 1
push_driver x 1
push_sequencer x 1
Cookbook-SequencesItems x 1
uvm_hdl_read x 2
ports x 3
factory-override-no-relevant-overrides x 1
contraint x 2
default x 2
Questa-QVIPs x 2
CHECK_ON_READ-BACKDOOR x 1
Cookbook-ConnectVirtual-Interface x 1
clock-error x 1
pulldown x 2
weak-values x 1
drive-strength x 2
simulation-speed x 1
memory-footprint x 1
2-state-logic x 1
library x 3
static-task-method x 2
coverpoint-multiple-ports x 1
parameter-queue x 2
UVM-Configuration x 3
sequence_item-has-null-sequencer x 3
uvm_tlm_analysis_fifo x 11
Can-software-drive-x-or-z-to-any-pin-of-DUT x 1
system-function x 4
packed-array x 4
reconfiguration x 1
IDFT x 1
Round-Robin-Arbiter x 5
NBA x 3
stability-of-a-signal x 2
uvm_config_db-set-from-sequence-and-get-in-tb_top x 1
uvm_sequencer x 4
post-synthesis-verification x 2
Modelling x 3
String-Bit-Type-Conversion x 1
UVM-RAL-back-door-peek x 2
Sync-reference-model-DUT x 1
pack_byes x 1
Web-Seminar x 17
Verification-IP x 7
Memory-Library x 1
uvm_reg_bit_bash_seq x 2
system-C x 1
systemc-verification x 4
Timescale-issue x 4
SVA-for-I2C-START-condition x 2
Unresolved-reference-to-object-cfg x 1
constraints-randomization-64-bit x 1
Default-bin x 2
system-verilog-dpi x 1
Comparing-arguments-of-two-sequences x 1
Specific-randomization-in-system-verilog-class x 3
cross-coverage-of-logical-expression x 2
UVM-type-override x 1
dynamic-hierarchy x 1
uvm_objection x 4
KillTheObjection x 1
abv x 2
assertion-coverage x 7
coverage-reporting x 1
assertion-reporting x 1
DUT-parameters x 5
Coverage-bins x 45
Coverage-hit-time x 1
Cookbook-TestbenchBuild x 1
array-of-defines x 3
Driver-to-scoreboard x 3
read-only-variable x 1
encapsulation x 3
instance-constant x 1
12-uvm_report_server-custom x 2
Queues-dynamic-arrays-delete-scoreboard x 1
RUN-time-error-while-using-SV-assertions x 1
timescale-pll x 1
error-flags x 2
priority-case x 2
Cookbook-DriverPipelined x 7
dist_exponential x 1
set_frontdoor x 1
frontdoor x 5
register-adapter x 5
uvm-register-model x 20
coverage-for-error-bits x 1
driver-to-coverage-analysis-port x 1
Sample x 1
gate-level-simulation x 2
static-constructor x 2
constraints-parser-systemverilog x 1
filing-a-bug-in-UVM x 1
constraint-sum-array x 1
nested-sequence x 2
mirror-value x 3
factory-registration x 2
A-agent_configuration-object-provided-to-constructor-is-not-valid-for-class-agent-Update-the-configuration-based-on-prior-Warning-messages x 1
convert-UVM-Testbench-into-OVM-testbench-environment x 1
systemVerilog-SDM x 1
constraints x 42
total-size x 1
uvm_topfind x 2
simulation-performance x 6
simulation-profiling x 1
Transport x 1
bit-slice-in-force-syntax x 3
unpack_ints x 1
valueplusargs x 3
testcase x 6
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System-Verilog-Verilog-File-Read-Operation x 4
File-IO x 7
global x 2
uvm_set_type_override x 2
hierarchical-task-call x 3
SPI x 4
array-methods x 5
iterator-index-querying x 1
error-vlog-7027 x 1
logical-shift-operators x 1
interface-array x 2
info x 1
time x 7
file x 3
Input-data-randomization x 1
Interfaces x 12
use-of-always-block-inside-ifdef-compiler-directive x 1
writememh x 2
rose-and-onehot x 2
constraint-null-array-error x 1
Assertion-variable-timing-check x 2
conditional-instantiation-depending-on-input-signal x 2
systemverilog-uvm x 60
multidimensional-array-systemverilog x 5
sequncer x 3
UVM-parameterized-agents-and-drivers x 2
Polymorhphism x 8
assert-property x 35
uvm_tlm_fifo x 2
syncronisation x 1
notation-uvm x 1
uvm_dpi_get_next_arg_c x 1
sformatf x 5
if-condition x 4
abort x 1
get x 3
uvm_pkg x 2
system-level-testcase x 1
block-level-testcase x 2
test-vector x 2
coverate x 1
OVM-coverage x 1
Cookbook-DriverUse-Models x 2
agent x 11
active x 1
max-array x 1
distribution x 3
system-verilog-lrm x 2
assertion-to-check-stability-throughout-simulation x 1
multiple-blocking_get_imp-get-task-single-component x 1
UVM-subscriber-monitor-list x 1
BURST x 2
mixed-array x 1
countones x 4
I2C x 6
Start x 2
SCL x 1
L1-cache x 1
uvm_component x 13
Cadence x 2
next-item-status-in-driver x 1
Dave-Rich x 17
Bus-interface x 12
BFM-tasks x 1
interface-modeports x 1
ovm_root x 1
Porting-legacy-verilog-code-to-UVM-classes x 1
UVM_BACKDOOR x 3
vsim-8239-Error-time x 1
randcase x 4
UVM_BASE_TEST_DERIVED_CLASS x 1
axi-bfm x 1
AXI-Verification-Driver-logic x 1
uvm_top_block-uvm_macro x 2
nested-sequence-and-factory-overrides x 1
Cookbook-SequencesGeneration x 2
CPU-UVM-verification-hex-code x 1
Connect_Phase x 5
Sequencer-to-Driver x 1
uvm_reg_fifo x 2
Sequence-systemverilog x 1
systemverlog-ref x 1
InterviewQuestions x 1
Multi-Master-Issue-in-test x 1
UVM-book x 1
immediately-overrides x 1
fdsq x 1
hang x 3
end-of-test x 2
RUN_TEST_NOCOMP_FACTORY_SET_TYPE_OVERRIDE_BY_TYPE x 1
UVM-SystemVerilog x 4
loading-memory x 1
string-to-array-coversion x 2
QUEUE_ARRAY x 1
processor-verification x 2
UVM-Reg-model-query x 3
UVM-topology-print x 1
UVM_NOCOMPARE x 1
Real-datatypes x 8
Real-comparision x 1
SystemVerilog--UVM x 1
Low-Power--UPF x 7
axi-driver x 2
parallel-execution-of-main_phase-and-run_phase x 2
Package_could_not_be_bound x 1
How-to-give-1step-sampling-for-concurrent-assertions x 1
When-is-Expanded-Time-Events-mode-in-Questasim-useful-for-analysis x 1
Signal-Relation x 1
Repeat-Untill x 1
Use-of-1-repeat-until x 1
always_comb x 7
always_ff x 4
Procedural-blocks x 1
time-scale x 1
equivalence-checking x 1
Coding-style x 1
Multiple-classes-in-a-file x 1
maximum-number-of-bins-in-a-cross x 1
flow-chart-for-the-uvm-code x 1
type_id x 1
why-need-dynamic-array-in-SV x 1
uvm_agent x 5
UPF x 4
UVM_REG-RACE-CONDITION x 1
uvm__factory x 1
Wilson-Research-Group-Study x 2
other-categories x 1
verification-concepts x 2
memory-verification x 3
factoryprint x 1
uvm_queue x 1
wildcard x 3
associative-array-methods x 3
Randomization-fail x 1
ref x 1
projects x 1
practical-learning x 1
Access-top-module-signal-inside-sequence x 2
SystemVerilog-PackedArray-Asociative x 2
set_report_id_verbosity x 1
typename-interface x 1
extended-driver x 1
extended-transaction x 3
find_override_by_name x 1
find_override_by_type x 1
child-class x 2
verilog-checker-with-a-stable-signal x 1
bufif0 x 1
pullup x 4
constraint-foreach-loop x 8
Emulation x 3
uvm-run_test x 1
locate-hdl-path x 2
register-read-mirror-set_check_on_read x 2
uvm_config_db-uvm_resource_db x 3
Assertion-system-verilog x 84
Cookbook-ConnectSequencer x 1
virtual-polymorphism x 2
Assertions-stable x 4
deterministic-sequence x 1
Scoreboard-request-grant-protocol x 1
push_back x 1
uvm_set_inst_override x 5
uvm_cmdline_processor x 4
namespace-REG x 1
Static-function x 4
Automatic-Function x 4
SVA-bind-different-hierarchy x 1
classes x 7
programming x 2
nested x 2
SystemVerilogAssertions x 2
create-macros-or-general-functions x 8
assetions x 2
constraint-for-loop x 3
part-select x 3
array-of-interfaces x 4
package-import-usage-in-environment-arch x 2
SVA-Arbiter x 4
randomisation x 2
extend-agent x 1
parameterization x 1
Illegal-virtual-interface-dereference x 3
uvm_max_quit_count x 2
UVM_PASSIVE x 1
passive-agent x 3
Queues-in-system-verilog x 5
dumplimit-dumplimit-waveform-vcd-systemverilog x 1
AHB-protocol-violations-check x 1
inside x 3
coverage_goal x 1
tlm-get-in-frontdoor-sequence x 1
Component-construction x 2
systemverilog-randomization x 4
Questa-Property-Checking x 1
UVM-11d-migration-12-DPI x 1
mutuality x 1
delay-range x 1
Verification-Flow x 1
uvm_svcmd_dpi x 1
string_compare x 1
compiler-directives x 2
uvm-subscriber-write- x 1
uvm_sequence-uvm_sequencer x 3
multiply-driven x 1
SystemVerilog-FunctionalCoverage x 62
Using-same-random-variables-arrays-in-two-different-modules x 1
memory x 7
set-config-object x 1
get-config-object x 1
uvm_analysis_export x 3
Covergroup-sampling x 2
unique-random-dynamic-array x 1
fork-join_any x 6
SV-assertion-for-random-clock-toggle x 1
test_base x 1
scoreboard-predictor-comparator x 2
UVM-register-mapping-pages x 2
vopt-2245 x 1
loop x 3
numbering x 1
Analog-behavioral-model x 1
modport-clocking-block x 3
uvm-scoreboard-monitor-print x 1
constrained-random-generation x 12
Assign-Delay x 5
IO-delay x 1
wire-delay x 1
fscanf-uvm-queue-vsim-8323 x 1
real-number-increment-calculation x 1
Clock-Domain-Crossing-Verification x 2
Questa-CDC x 2
queue-matching x 1
queue-deletion x 2
sequence-fscanf-system-verilog x 1
casting-copy-compare x 1
system-verilog-parametrized-classes x 2
sampling-point x 1
max_size x 1
connection x 2
Conditional-constraint x 2
inside-inline-constraint x 1
System-Veriilog-Events x 2
concatenation-array x 1
Parameterised-interface x 2
FLI x 1
systemverilog-Arrays x 72
pass-argument-by-ref x 2
system-verilog-system-verilog-assertions x 2
urandom x 6
unpacked-array-of-packed-array x 2
functions-arguments x 1
tlm-mailbox x 1
scoreboard-queues-comparator-fscanf x 1
timescale-uvm_info x 2
uvm-printing-topology x 2
clocking-blocks x 3
procedural-assignment x 2
continuous-assignment x 6
multiple-drivers x 3
queue-fscanf-read-uvm x 1
downcast x 2
clock-block x 1
environment x 6
axi x 8
axi_cache x 1
match-testcase_name-pattern-in-virtual-seq_lib x 1
randsequence-SV x 1
random-generator x 1
UVM-extension-transaction x 1
constraints-for-random-variables x 7
UVM-phase-scheduler x 2
UVM-Phase-customization x 2
Timing-Testbench x 1
Single-Transactions-and-Multiple-Sequence x 1
illegal-use-of-modport x 1
synchronous-fifo-using-queue x 1
Bind-Factory-UVM x 3
bus-functional-model x 2
testbench-architecture x 1
througout x 1
UVM-DUT-connection x 2
SystemVerilog-modport x 4
Interface-modport x 3
paging x 1
objection-syntax x 1
illegal-declaration x 1
SystemVerilog-Syntax x 5
randmize x 1
Assertions-VHDL x 1
coverage-system-verilog-cover-bins x 7
test-and-sequence x 1
Timing-checks-using-skew x 2
uvm-systemC x 1
UVM_REG-mirror-write x 1
agent-configuration-file x 2
concantenation x 1
sequence-to-scoreboard x 1
assert-final x 1
generic-code x 1
generic-coverage x 1
partial-write x 1
memory-coverage x 1
pre_configure_phase x 1
division x 3
rounding x 3
bitstoreal x 3
always-blocks x 5
conceptual x 1
sensitivity-list x 3
event-scheduling x 4
config x 5
config-sequence x 1
system-verilog-module x 3
SV-Constraint-Solver x 4
Alternate-register x 1
modular x 1
reusable x 2
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-lca-warning x 1
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single-key x 1
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SIPO x 1
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cher x 1
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FWRITE x 3
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DAC-2019 x 1
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hello_world x 1
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xcelium x 2
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LTL x 1
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arbieter x 1
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UVM_SEQ_ARB_STRICT_FIFO x 1
Sequencer-lock x 1
Error-suppressible x 1
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printstatements x 1
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64-bit x 1
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Sva-strong x 1
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C-MODEL-GOLDEN-MODEL x 1
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errorXMRE x 1
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UVM-UVMRAL x 2
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uvm_color x 1
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Sliding-Patterns x 1
Sliding_0 x 1
Sliding_1 x 1
Sliding-Pattern x 1
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post_body x 1
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force-release x 3
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Facade x 1
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mutilple-agent-for-the-same-bus-protcol x 1
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ID x 1
axi-uvmf x 1
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merge x 1
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limit-SVA x 1
Dynamic-Address-Mapping-from-Cookbook x 1
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Question-related-to-add_submap x 1
cocotb x 1
Cookbook-RegistersIntegrating x 1
task-input-initialization x 1
Suggestions-for-class-definition-for-user_item x 1
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Function-inside-constraint x 1
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SystemVerilog-force x 1
DUT-internal-signal x 1
SV-interface-bind-to-vhdl x 1
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rand-constraint x 1
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fread-fscanf-file x 1
cast-factory x 1
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Error-using-a-create-method x 1
pcie-protocol-explanation x 1
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UVM-RAL-SEQUENCE x 2
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RAL-in-scoreboard x 1
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otp x 1
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sector x 1
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AXIS x 1
Memory-Leak x 1
UVM-bit_bash x 1
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RTL-bug x 1
issueRALread0 x 1
AHB-VIP-interface-within-Multi-Layer-Bus x 1
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Constraint-for-Octal-Addition x 1
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Compilation-units x 1
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-UVM-warnings-disable x 12
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Response x 2
Request x 1
response-before-request x 1
UVM-Passing-value-from-a-driver-to-a-sequence x 1
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range-coverage-bins-empty x 1
video x 1
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SVA-Variable x 1
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Between-the-Edge-of-busy x 1
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Coverage-plan x 1
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two-sets-of-different-transaction x 1
sv-classes x 3
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Finite-state-machine x 1
hierarchical-name-component-lookup-failed x 1
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UVM-fatal-error-interfaces x 1
Scoreboard-implementation-using-analysis x 1
Clk-jitter x 1
refrence-model x 1
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UVM-sequencer-p_sequencer x 1
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register-masking x 1
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Ben_Cohen x 2
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ral_model x 2
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append x 1
Register x 1
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Functional-coverage-wildcard x 1
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auto-prediction x 1
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SV3 x 1
prbsq x 1
qprbs x 1
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f-for-Real-Numbers x 1
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WSTRB x 1
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Cookbook-OVMEmulationExample x 1
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uvm-create x 1
Working-of-Multiple-edge-in-antecedent x 1
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riscv-uvm x 2
UVM_ERROR-TEST_DONE_NOHIER x 1
UML x 1
UVM-SV-DUT-backdoor x 1
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experience x 1
Transactionpacket-to-wiggling-pins x 1
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time-slot x 1
depth x 1
Difference-between--0--and----in-Assertions x 1
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UVM-array-analysis-imp x 1
uvm-phase-report_phase x 1
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Assertion-signal-a-and-signal-b x 1
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quartus x 1
cyclone-II x 1
UVMwrite_functionround-robin x 1
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cbAssertionFailure x 1
vpiProperty x 1
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Check-for-Illegal-State-Transition x 1
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C-programming-Verification-Hardware x 3
reset-broadcasting x 1
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Path-as-parameter-to-DUT x 1
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compiler x 1
time0 x 1
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UVMconfiguration x 1
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ISO26262 x 1
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UVM-IN-ORDER-COMPARATOR x 1
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REQ-FIFO x 1
SVA-Property x 1
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svcoverage x 2
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Unable-to-access-packet-in-scoreboard x 1
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CSA-Tree x 1
42-Compressors x 1
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DDR4-SDRAM x 1
DPIC x 1
2-state-data-types x 1
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CONNECTION-ERROR x 1
HANDLE-CREATION-ISSUE x 1
UVM-SVrand_mode x 1
Parellel-case-and-full-case x 1
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FPV x 1
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divisible-by-5 x 1
UVM-RALTHROUGH-DRIVER x 1
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Achieving-Dynamic-delays-in-SVA-using-subroutine x 1
Xilinx-IPs x 1
transceiver x 1
Understanding-intersect-operator x 1
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Singular x 1
1-physical-ral-address-two-offsetsInterface x 1
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typedef-usage x 1
Generic-reference-of x 1
CPF x 1
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SVA-with-multiple-clocks x 1
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Are-timescale-applicable-for-Classes- x 1
Want-to-capture-data-with-2-different-clock-in-monitor x 1
Knight x 1
tour x 1
Data-Mismatched-in-scoreboard x 1
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UVM-field-macros x 1
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UVM_MAX_QUIT_COUNT-being-overridden x 1
Logic-to-generate-powers-of-2-without-using-constraints x 1
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A-few-questions-on-SVA x 3
NETLIST x 1
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UVMLAYERINGSEQUENCE x 1
Assertion-for-data-toggle x 1
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Regarding-const-cast x 1
AssemblyLanguage x 1
ArmV8 x 1
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phy x 1
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ctest-sv-sv-dpi x 1
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base-sequence x 1
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CDC-assert x 1
Recursive-property-call x 1
vpi-dpi-deposit-force x 1
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System-verilog-assertion-sequence-logic x 1
always_comb-force-release x 1
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Regarding-simple-immediate-assertion x 1
processor x 1
project x 1
self-learning x 1
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assign-statement x 1
frame x 1
systemverilog-interfaces x 1
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severity_overrride x 1
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does-it-ever-match- x 1
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Systemverilog-mode x 1
RAL-Scoreboard x 1
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Is-it-possible-to-trigger-pass-action-block-on-execution-of-finish- x 1
multiple-reset x 1
How-does-randomize-work-in-the-following-case x 1
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Modeling-dynamic-repeat-range x 1
Clarification-regarding-LRM-161222-Nondegeneracy x 1
Working-of-s_alwaysNM x 1
UVM-GP x 1
Distribute-constraint-with-coverage x 1
Singleton x 1
UVM-uvm-transaction x 1
field x 1
SystemVerilog-SVA x 1
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Pedantic-Errors x 1
Significance-of-parenthesis-in-SVA-evaluation x 1
Meaning-of x 1
Multiple-clocking-events x 1
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18002 x 1
Accellera x 1
Verification-Cookbook x 2
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DVClub x 1
survey x 1
Ray-Salemi x 1
Questa-CoverCheck x 1
Mark-Eslinger x 1
Joe-Hupcey-III x 1
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Assertions-WITHIN-INTERSECT x 1
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SVA-Ben-paper x 1
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SVA-to-check-next-read-request x 1
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LRM-Correction x 1
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Equivalent-expression-for-b0 x 1
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ral_coverage x 1
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API x 1
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C x 1
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Array x 1
muku_kr x 1