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  • All Topics
    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IP
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • UVMF - One Bite at a Time
      • Introduction to UVM
      • Basic UVM
      • UVM Debug
      • Advanced UVM
      • UVM Connect

    • Featured Courses

      • Portable Stimulus Basics
      • Introduction to DO-254
      • SystemVerilog OOP for UVM Verification
      • Power Aware Verification
      • Power Aware CDC Verification
      • Assertion-Based Verification
      • Metrics in SoC Verification

    • Additional Courses

      • Clock-Domain Crossing Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal Coverage
      • Formal-Based Technology: Automatic Formal Solutions
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
      • Solutions
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      • Search
      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
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      • SystemVerilog Forum

    • Coverage Forum

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      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • AMS Forum
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizon - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Upcoming & Featured Events

      • Correct Common RTL Issues - March 27th
      • Advance Your Verification Methodology - April 9th | Westford, MA
      • Low Power Verification Forum
      • Portable Simulus
      • Events Calendar

    • On Demand Seminars

      • UVM 1800.2 & Updated UVM Cookbook
      • Debug
      • FPGA Verification
      • Stimulus Generation
      • All On-Demand Seminars

    • Recording Archive

      • Portable Stimulus from IP to SoC
      • Wilson Research Group - 2018 Results
      • DAC & DVCon
      • UVM Forum
      • All Recordings

    • Mentor Training Center

      • SystemVerilog for Verification
      • SystemVerilog UVM
      • SystemVerilog UVM Advanced
      • Instructor-led Training

    • Mentor Learning Center

      • SystemVerilog Advanced OOP
      • UVM Transactions and Sequences
      • UVM Monitors and Agents
      • Functional Verification Library
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification Horizons Blog
      • Academy News
      • Technical Resources

    • Verification Horizons Publication

      • Verification Horizons - February 2019
      • Verification Horizons - November 2018
      • Verification Horizons - June 2018
      • Verification Horizons - March 2018
      • Issue Archive

    • About Us

      • Verification Academy Overview
      • Subject Matter Experts
      • Contact Us

    • Training

      • Questa® & ModelSim®
      • SystemVerilog
      • Functional Verification Library
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Tag List

  • #systemverilog 230
  • uvm 143
  • #uvm 112
  • UVM 87
  • System Verilog 78
  • assertion 76
  • SVA 64
  • Assertions 52
  • RAL 50
  • systemverilog 47
  • Assertion system verilog 41
  • #SystemVerilog #FunctionalCoverage 35
  • constraint 35
  • uvm_config_db 35
  • constraint randomization 31
  • interface 30
  • DPI 30
  • sequence 28
  • coverage 28
  • SystemVerilog 27
  • #systemverilog #Arrays 27
  • ovm 24
  • #UVM #RAL 24
  • scoreboard 23
  • class 23
  • functional coverage 22
  • uvm_sequence 20
  • uvm_reg 20
  • assertion systemverilog 20
  • SVA Assertion 19
  • Advanced UVM Register 18
  • cross coverage 18
  • virtual sequence 18
  • queue 17
  • SV 17
  • system verilog assertion SVA 17
  • assert property 16
  • config_db 16
  • Package 16
  • virtual interface 16
  • randomization 16
  • Dynamic Array 15
  • #randomization 15
  • array randomization 15
  • bind 15
  • Formal Verification 15
  • analysis port 14
  • Verilog 14
  • OOPS 14
  • Verification Horizons 14
  • Inheritance 14
  • Constraint SystemVerilog 14
  • coverpoint 14
  • Web Seminar 13
  • Polymorphism 13
  • Learning System Verilog 13
  • task 13
  • associative array 13
  • driver 13
  • Constraint random verification 12
  • parameter 12
  • sequencer 12
  • mailbox 12
  • system verilog assertion 12
  • constraints 12
  • $cast 12
  • clock 12
  • tlm 12
  • Bus interface 11
  • p_sequencer 11
  • ASSERTION BASED VERIFICATION 11
  • code coverage 11
  • virtual sequencer 11
  • factory 11
  • systemc 11
  • uvm_info 11
  • assert 11
  • UVM uvm_test 10
  • Cookbook: UVM 10
  • VIP 10
  • Seminar 10
  • array 10
  • Coverage bins 10
  • uvm register model 9
  • randomization constraints 9
  • uvm_config_db #(...)::get() 9
  • event 9
  • unpacked array 9
  • Portable Stimulus 9
  • questasim 9
  • event trigger 9
  • constrained random generation 9
  • property 9
  • modport 9
  • Randomize 9
  • configuration 9
  • functions in system verilog 9
  • Race condition 9
  • VHDL 9
  • covergroup 9
  • UVM phases 9
  • Clocking Block 8
  • uvm_error 8
  • uvm_tlm_analysis_fifo 8
  • #uvm #verilog 8
  • class handle 8
  • Event Regions 8
  • $display 8
  • Cookbook: Cookbook Code Examples 8
  • dynamic arrays 8
  • dist 8
  • Verification 8
  • sequence and sequencer 8
  • field macros 8
  • configdb 8
  • uvm_reg_map 8
  • Cookbook: Phasing 8
  • checker 8
  • dpi-c 8
  • function 8
  • uvm_driver 8
  • questa 8
  • uvm_reg_block 8
  • BFM 8
  • UVM_VERBOSITY 7
  • system verilog constraints 7
  • System Verilog Virtual Functions 7
  • uvm_object 7
  • UVM_PHASE 7
  • #queues 7
  • wait statement 7
  • backdoor 7
  • agent 7
  • static method 7
  • Cookbook: Registers/ModelStructure 7
  • TLM FIFO related 7
  • Parameterized classes 7
  • 2D array SystemVerilog 7
  • SOC verification 7
  • constraints systemverilog 7
  • multiple agents 7
  • override 7
  • uvm uvm_config_db 7
  • Verification Academy Technology Series 7
  • Checkers 7
  • Systemverilog Assertion 7
  • uvm_mem 7
  • Constructor 7
  • uvm_sequence_item 7
  • fork join 7
  • introduction to system verilog 7
  • reset 7
  • SystemC UVMConnect 6
  • formal verification assertion 6
  • UVM callback 6
  • concurrent assertion 6
  • Clock generator 6
  • uvm_event 6
  • Cookbook: Scoreboards 6
  • system verilog assertions 6
  • Active UVM models 6
  • uvm ral 6
  • set_type_override_by_type 6
  • UVM Sequence Library 6
  • #systemverilog #Arrays #packedarrays #unpackedarrays 6
  • enum 6
  • registers 6
  • deep copy 6
  • timing checks 6
  • Parameters 6
  • create() and new() 6
  • constraint dist 6
  • actual interface 6
  • uvm_component 6
  • UVM Driver 6
  • generate 6
  • for loop 6
  • uvm virtual interface 6
  • casting 6
  • monitor 6
  • assertion coverage 6
  • FATAL ERROR 6
  • import 6
  • fifo 6
  • sequences 6
  • generate block 6
  • system verilog testbench 6
  • Cookbook: Coverage/Testplan to Functional Coverage 6
  • Real datatypes 6
  • accessing the associative array elements 6
  • uvm_analysis_imp 6
  • UVM Configuration database 6
  • RAL register UVM 6
  • Questa® Formal Verification Apps 6
  • UVM MEMORY MODELING 5
  • Flow UVM 5
  • fork join in loop 5
  • constraints for random variables 5
  • vcs 5
  • set_inst_override 5
  • Transition Coverage. 5
  • set_type_override 5
  • driver monitor 5
  • systemverilog datatypes 5
  • UVM_reg_field 5
  • parameterized 5
  • clone() 5
  • real numbers 5
  • UVM monitor 5
  • Register abstraction Layer 5
  • UVM_OBJECT and UVM_COMPONENT 5
  • start_item 5
  • glitch 5
  • cover groups 5
  • uvm_reg_adapter 5
  • Systemverilog DPI 5
  • Delay 5
  • function new 5
  • Resource_db 5
  • hierarchical reference 5
  • build_phase 5
  • functional verification 5
  • UVM Factory Registration 5
  • Arbitration 5
  • create macros or general functions 5
  • run_phase() 5
  • #verilog 5
  • interface class 5
  • Assertion binding 5
  • typedef 5
  • always_comb 5
  • File reading 5
  • Overridding parameterized class 5
  • fork join_any 5
  • macros 5
  • Verification IP 5
  • uvm register 5
  • semaphore 5
  • classes 5
  • Methodology 5
  • Extended Class 5
  • array interface parameterized 5
  • uvm_monitor 5
  • Compilation Error 5
  • enumeration datatype 5
  • memory 5
  • argument pass by ref 5
  • sprint 5
  • uvm agent 5
  • Debug 5
  • Cookbook: Registers 5
  • unique 5
  • Mirrored values and desired values in UVM RAL 5
  • modelsim 5
  • constraint foreach loop 5
  • uvc 5
  • illegal bins 5
  • +uvm_set_severity 5
  • predict 5
  • Queues 5
  • uvm_transaction 5
  • reference model 5
  • Use of virtual sequence and virtual sequencer. 5
  • testbench 5
  • start() in sequencer 5
  • UVMConnect 5
  • binding in SV 5
  • coverage system verilog cover bins 5
  • File I/O 5
  • initialization 4
  • Cookbook: Sequences/Slave 4
  • program block 4
  • constraint array 4
  • array of covergroups 4
  • Command Line Processing 4
  • new function 4
  • continuous assignment 4
  • SEED 4
  • FSM 4
  • Cookbook: Driver/Pipelined 4
  • Multiple Sequences 4
  • function coverage 4
  • bus2reg 4
  • Queues in system verilog 4
  • Cookbook: Sequences/Stopping 4
  • run_phase 4
  • raise_objection and drop_objection 4
  • module 4
  • RAL UVM adapter 4
  • randomization error 4
  • timeout 4
  • Sequence Layering 4
  • timeunit 4
  • coverage transition bins 4
  • uvm_do macros 4
  • gcc 4
  • testbench environment 4
  • Interfaces 4
  • DPI import 4
  • synthesize 4
  • uvm_warning 4
  • constraint solver 4
  • set_config_object 4
  • compilation 4
  • Dave Rich 4
  • frontdoor 4
  • error injection 4
  • return data 4
  • Assertions using Generate Block 4
  • DUT 4
  • Xilinx 4
  • UVM TLM Analysis port 4
  • tlm_fifo 4
  • Low Power | UPF 4
  • $realtime 4
  • register adapter 4
  • ignore_bins 4
  • assert(std::randomize(variable)) 4
  • static 4
  • #coverage 4
  • multiple interface 4
  • uvm_reg_predictor 4
  • on the fly reset 4
  • uvm_sequencer 4
  • events 4
  • inherited_classes 4
  • sequencer and driver 4
  • Cookbook: Registers/SequenceExamples 4
  • uvm_factory 4
  • SV Constraint Solver 4
  • for loop fork join_none 4
  • UVM phase methods 4
  • comparator 4
  • transactions 4
  • regressions 4
  • uvm_reg frontdoor backdoor 4
  • sequence body() 4
  • +uvm_set_inst_override 4
  • UVM system verilog 4
  • TLM ports 4
  • first_match 4
  • generate macro `define 4
  • Constraining a random variable 4
  • SV DPI 4
  • array methods 4
  • cross 4
  • Factory Overrides 4
  • automatic variables 4
  • array slicing 4
  • end of test mechanism in UVM 4
  • randc 4
  • Advanced Verification 4
  • Course 4
  • uvm error 4
  • reuse 4
  • uvm_env 4
  • UPF + power aware 4
  • interface in system verilog 4
  • System Verilog Verilog File Read Operation 4
  • packed array 4
  • uvm_analysis_imp and uvm_analysis_export 4
  • Polymorhphism 4
  • UVM reuse 4
  • sequence control 4
  • config 4
  • string 4
  • uvm connect 4
  • Cookbook: Registers/BackdoorAccess 4
  • TLM 2.0 3
  • Write 3
  • singleton class 3
  • task argument 3
  • #systemverilog#deepcopy 3
  • Generating sequences 3
  • urandom 3
  • raise objection 3
  • uvm overriding 3
  • cross coverage bins 3
  • force signal 3
  • local variables 3
  • Cookbook: Testbench/Blocklevel 3
  • assert #0 3
  • UVM1.1d documentation source code 3
  • UVM raise and drop objection 3
  • end_tr 3
  • Cookbook: Analysis 3
  • environment 3
  • Null pointer dereference 3
  • DPI error 3
  • uvm_cmdline_processor 3
  • signed 3
  • randomize with 3
  • simulation performance 3
  • HDL designer systemverilog interface 3
  • uvm_scoreboard 3
  • multithreading 3
  • delay timescale timeunit systemverilog 3
  • Questa® Power Aware Simulator 3
  • initial_block 3
  • clocking block event 3
  • Expression Coverage 3
  • uvm_field_int 3
  • Abstract class 3
  • sv env 3
  • Calling Sequence inside a sequence 3
  • array of defines 3
  • UVM Predictor UVM_REG_MAP 3
  • $monitor 3
  • get_next_item 3
  • register layer 3
  • Bind Factory UVM 3
  • main_phase 3
  • implication operator 3
  • SIGSEGV 3
  • uvm run_phase 3
  • Wilson Research Group Study 3
  • UVM Coverage 3
  • parameterized class 3
  • reading .txt file in UVM driver 3
  • Cookbook: Sequences/VirtualSequencer 3
  • System verilog for loop 3
  • I2C 3
  • raise_objection in pre_body() 3
  • $past 3
  • verbosity 3
  • waveform 3
  • Multi-dimensional arrays 3
  • cover property 3
  • grab regmodel sequencer 3
  • UVM Configuration 3
  • timeout value 3
  • reporting 3
  • ucdb 3
  • UVM sequence UVM hierachy 3
  • Function new() 3
  • Infinite loop 3
  • finish_item 3
  • inout 3
  • `define macro 3
  • array interface in uvm_config_db 3
  • Abstract interface 3
  • $display hierarchy 3
  • get_config_object 3
  • begin_tr 3
  • UVM RAL Backdoor Write hdl_path 3
  • enumerated 3
  • error 3
  • static property 3
  • #configuration 3
  • Questasim 10.0b 3
  • always_ff 3
  • wire 3
  • systemverilog mailbox 3
  • UCIS 3
  • uvm_sequence uvm_sequencer 3
  • structure and union 3
  • hierarchical task call 3
  • Connect_Phase 3
  • Cookbook: Sequences/Hierarchy 3
  • #uvm #callback 3
  • SV constraint 3
  • uvm_hdl_force 3
  • constraint for loop 3
  • passive agent 3
  • logic 3
  • fork join_any fork join_none 3
  • System-verilog 3
  • UVM 1.2 3
  • convert 3
  • Pipelined 3
  • shallow copy 3
  • agents 3
  • Mapping data types 3
  • Cookbook: Config/ConfiguringSequences 3
  • implementation 3
  • class issue 3
  • uvm register w1c 3
  • ports 3
  • Timescale issue 3
  • Analog behavioral model 3
  • Cookbook: Questa/CompilingUVM 3
  • stuck between run_phase and extract_phase 3
  • tlm port 3
  • mirrored value 3
  • Callbacks 3
  • test 3
  • passive agent set_drain_time 3
  • OVM Systemverilog 3
  • get set 3
  • performance 3
  • axi amba protocol 3
  • fork join_none multiple threads 3
  • LRM 3
  • uvm_object_utils 3
  • non static method 3
  • binding 3
  • AHB 3
  • UVM Register Built-in sequence 3
  • thread 3
  • static variable 3
  • SystemVerilog Constructs 3
  • Streaming Operator 3
  • Harry Foster 3
  • type_id::create() 3
  • Virtual methods 3
  • uvm_reg_sequence 3
  • Assertion-Based Verification 3
  • memory verification 3
  • parameterized interface 3
  • Cookbook: Registers/StimulusAbstraction 3
  • connect_phase in uvm 3
  • Parent to an object 3
  • c 3
  • program 3
  • pass by reference 3
  • asynchronous 3
  • UPF 3
  • interface connections 3
  • system verilog module 3
  • fork 3
  • $fell 3
  • ASIC/IC Verification Trends 3
  • $root 3
  • wait_modified() 3
  • get_response 3
  • $stable 3
  • uvm_printer 3
  • questa formal 3
  • AHB burst 3
  • master and slave 3
  • systemverilog assertion concurrent 3
  • UVM Reporting 3
  • VIP integration 3
  • Blocking 3
  • AMBA AXI 3
  • systemVerilog Queue Scoreboard UVM 3
  • DUT parameters 3
  • API to access Ral model in OVM 3
  • derived class 3
  • `uvm_do_with 3
  • pullup 3
  • SCE-MI for Co-Emulation 3
  • SVA Arbiter 3
  • compare 3
  • put_port 3
  • randc usage constraint 3
  • assertion ##1 3
  • Cookbook: Agent 3
  • assertion errors 3
  • virtual 3
  • uvm_report_server 3
  • uvm events synchronisation 2
  • Cookbook: Resources/Config DB 2
  • procedural assignment 2
  • RTL 2
  • export DPI-C 2
  • override parameterized 2
  • associative array inline constraint 2
  • ncelab: *E 2
  • runtime speed 2
  • library 2
  • VRM 2
  • sv dpi export 2
  • interface binding 2
  • coding guidelines 2
  • factory overriding at run time 2
  • Interface Instantiation 2
  • system verilog package compilation 2
  • Efficient way to cross transition cover points 2
  • arrays 2
  • base class 2
  • Scheduling semantics 2
  • Regarding memory allocation of an object in SV 2
  • ifdef 2
  • BFM interface tasks sequence 2
  • testcase 2
  • $rose 2
  • Compile UVM 1.2 in Windos 64 bit 2
  • starting_phase in uvm 2
  • uvm automated testbench 2
  • randcase 2
  • Assertion : How to handle when delay in the signal. 2
  • get_type 2
  • Bind assertions to specific instances 2
  • uvm randomization 2
  • sverilog vcs systemverilog 2
  • uvm_analysis_port 2
  • Bins 2
  • Questa inFact 2
  • frequency 2
  • #bind 2
  • Related to UVM phases 2
  • uvm_registry 2
  • stimulus in system verilog 2
  • uvm components compilation 2
  • always blocks 2
  • wildcard 2
  • Driver to scoreboard 2
  • BNF 1800 2012 2
  • sequence killed or finished 2
  • Cookbook: OVM/Phasing 2
  • predictor 2
  • within 2
  • indirect_addressing 2
  • OOP 2
  • syntax_error 2
  • simulation time 2
  • Questa® inFact 2
  • Cookbook: Registers/Integration 2
  • TLM connection topology 2
  • print transaction 2
  • covergroup coverpoint cross coverage foreach 2
  • System Veriilog Events 2
  • m_uvm_get_type_name_func 2
  • const 2
  • uvm_tlm_fifo 2
  • programming 2
  • extern task of a class 2
  • Recording 2
  • genvar 2
  • modelsim altera starter edition 2
  • cross coverage bins constraints 2
  • locate hdl path 2
  • test plan 2
  • peek 2
  • $countones 2
  • VCD 2
  • factory registration 2
  • ELBERR: Error during elaboration (status 1) 2
  • set_config_ 2
  • Scheduling semantics in System Verilog 2
  • fork join join_none 2
  • loop 2
  • iff 2
  • DO-254 2
  • transitions 2
  • Formal Apps 2
  • UVM randomization stability 2
  • data flow synchronization 2
  • $time 2
  • equivalence checking 2
  • random stability 2
  • shuffle 2
  • grab 2
  • multiple 2
  • Frocing the DUT signal 2
  • factory::create 2
  • systemverilog checker 2
  • object 2
  • uvm_comparer 2
  • Driver and Monitor in system verilog 2
  • multiple environment uvm 2
  • typed constructor call 2
  • default value 2
  • item 2
  • string concatenation 2
  • include 2
  • Clock domain crossing 2
  • Synchronization 2
  • configure monitor random items 2
  • industry standard 2
  • clock generator using classes 2
  • RNM 2
  • connect sequencer 2
  • super.build_phase(phase); 2
  • inline constraints handling 2
  • assigning class instances 2
  • Mirror Model 2
  • Cookbook: Sequences 2
  • vopt 2
  • instance name 2
  • SOC 2
  • unpacked array of packed array 2
  • sequence_library 2
  • Generic clock generation 2
  • abstract driver 2
  • UVM monitor-scoreboard sync issue 2
  • `UVM_INFO component name meaningless 2
  • sv interfaces 2
  • array of interfaces 2
  • UVM verification steps 2
  • disable 2
  • setting default sequence in tests 2
  • get 2
  • protocol checks using assertions 2
  • Access top module signal inside sequence 2
  • UVM parameterized agents and drivers 2
  • cast p_sequencer m_sequencer 2
  • push_pull 2
  • active/passive agent configuration 2
  • phase 2
  • SVA bind 2
  • uvm_objection 2
  • Get_next_item called twice without item_done or get in between 2
  • macro nested 2
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