Topics tagged SystemVerilog

Topic	Replies	Views	Activity
Bug (?) in uvm_pool UVM SystemVerilog , UVM , uvm_event_pool	0	4	March 13, 2026
SV Assertions using $past() SystemVerilog SystemVerilog , assertion	2	68	February 18, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? UVM SystemVerilog , UVM	2	40	February 18, 2026
Formal arguments to properties / sequences SystemVerilog SystemVerilog , SVA , paramterized-properties	1	25	February 13, 2026
A query about push_back and pop_front SystemVerilog SystemVerilog , UVM	10	3974	February 12, 2026
SVA sampling of always( a ##1 b[->1] ) SystemVerilog SystemVerilog , concurrent-assertion , Embdedded-Concurrent-assertion , always-property	6	54	February 8, 2026
Vending Machine in System Verilog SystemVerilog SystemVerilog , System-Verilog , Polymorphism , SV , OOPS , constraint-randomization	2	203	February 2, 2026
Constraint Randomization Interview Question SystemVerilog SystemVerilog	22	5612	January 25, 2026
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	24	12121	January 20, 2026
Assertion question :- SystemVerilog SystemVerilog , assertion , System-Verilog , systemverilogassertionSVA	9	554	January 18, 2026
SystemVerilog constraint: unique addr across array of structs without auxiliary array SystemVerilog SystemVerilog , constraint-randomization , unique	3	109	January 9, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	658	January 7, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	64	January 5, 2026
Sequence which admits : No match v/s Hard Zero SystemVerilog SystemVerilog , assertion , SVA	8	418	December 27, 2023
Semaphore put method question SystemVerilog SystemVerilog , System-Verilog , semaphore-keys , semaphore-with-multiple-keys	5	434	December 28, 2025
SVA to check a N-stage synchronizer output SystemVerilog SystemVerilog , assertion , System-Verilog , SVA , SVA-Assertion	9	103	December 18, 2025
Connection using modports with different signals SystemVerilog SystemVerilog , modport , interface	6	68	December 12, 2025
Deep copy using shallow copy SystemVerilog SystemVerilog	1	77	December 6, 2025
Once a certain sequence occurs that another seq shouldn't occur till simulation ends SystemVerilog SystemVerilog , Once-a-certain-sequence-occurs-that-another-seq-shouldnt-occur-till-simulation-ends	8	676	December 4, 2025
Adding and deleting elements of dynamic type at same time SystemVerilog SystemVerilog , Queues , Dynamic-Array	2	85	November 29, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	92	November 17, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	89	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	51	November 12, 2025
Resume simulation when any 2 threads out of 3 get completed within fork-join_any SystemVerilog SystemVerilog , fork-join_any	9	4254	November 12, 2025
Question regarding followed by operator in SVA (#-# and #=# SystemVerilog SystemVerilog , SVA , SVA-Assertion	0	67	November 11, 2025
System verilog constraint help SystemVerilog SystemVerilog , constraint-randomization	2	134	November 11, 2025
Chained Implications in SVA SystemVerilog SystemVerilog , Coverage , assertion , SVA , axi , AHB	0	71	November 3, 2025
Why only ##1 (single delay operator) used in the case of multiple clock sequences? SystemVerilog SystemVerilog , assertion	2	685	November 3, 2025
restricting sequence as long as one variable is asserted SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	88	November 2, 2025
Paper: Understanding SVA Degeneracy SystemVerilog SystemVerilog , SystemVerilog-SVA	9	614	October 29, 2025