Topics tagged SystemVerilog

Topic	Replies	Views	Activity
How text macro affect inside and outside pkg? SystemVerilog SystemVerilog , compilation-macro	2	6	April 27, 2024
Performance problem SystemVerilog SystemVerilog	3	50	April 24, 2024
Constraint Randomization Interview Question SystemVerilog SystemVerilog	17	4259	April 24, 2024
Vopt-13412) Virtual methods of an object or built-in method are not allowed in event control expressions SystemVerilog SystemVerilog	1	23	April 23, 2024
Arr.sum() - constraint SystemVerilog SystemVerilog , systemverilog-constraint	1	39	April 23, 2024
What is the general difference between static and dynamic events in SystemVerilog? SystemVerilog SystemVerilog	3	904	April 23, 2024
N Queen Board Problem in SV Constraint SystemVerilog SystemVerilog , systemverilog-constraint , array-reducation , Constraint-Interview-Question	7	579	April 23, 2024
How to pass delay through a variable in assertion SystemVerilog SystemVerilog	7	1997	April 23, 2024
Using sequence method triggered within Sampled value functions SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	3	38	April 20, 2024
Empty bin warning for disabled cover point Coverage SystemVerilog , Coverage	1	27	April 19, 2024
Elaboration time constant for enumerated type.num() SystemVerilog SystemVerilog	2	31	April 18, 2024
Parameter type in interface SystemVerilog SystemVerilog , interface	1	36	April 16, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	976	April 16, 2024
Illegal range in part select SystemVerilog SystemVerilog	10	4752	April 16, 2024
APB state operation SystemVerilog SystemVerilog	0	25	April 15, 2024
NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED SystemVerilog SystemVerilog , virtual-interface-scoreboard-uvm	5	352	April 15, 2024
Constraint array SystemVerilog SystemVerilog , systemverilog-constraint	2	87	April 12, 2024
Function New Constructor UVM SystemVerilog , UVM	1	48	April 11, 2024
How do I avoid using #0 in an interface monitor SystemVerilog SystemVerilog , UVM	3	62	April 10, 2024
How the within syntax is working in SVA SystemVerilog SystemVerilog , assertion , SVA	7	2169	April 10, 2024
System Verilog Fine grain Process SystemVerilog SystemVerilog	2	59	April 9, 2024
Backdor access without using RAL model SystemVerilog SystemVerilog	3	64	April 8, 2024
Write a constraint for polindrome (say 32 bit)? SystemVerilog SystemVerilog , constraint	15	6281	April 7, 2024
Understanding a Bug in the Distribution Constraint SystemVerilog SystemVerilog	4	77	April 8, 2024
DUT reference model location? UVM SystemVerilog , UVM	2	63	April 7, 2024
Best Practice for Unit Tests Extending Chip-Level Tests UVM SystemVerilog , Inheritance	1	59	April 6, 2024
Solve before constraint used with implication operator SystemVerilog SystemVerilog , constraint-randomization , systemverilog-constraint	7	75	April 6, 2024
Checking clock period using system verilog assertion SystemVerilog SystemVerilog , assertion	30	51928	April 5, 2024
Passing variables to a subroutine on sequence match SystemVerilog SystemVerilog , assertion , SVA	2	81	April 5, 2024
LRM :: "Assertion evaluation does not wait on or receive data back from any attached subroutine" SystemVerilog SystemVerilog , assertion , SVA , SVA-Assertion	1	35	April 5, 2024