Need help with randomizing the data width of sequence items

UVM
,
1

Hi guys,
I’m trying to write a sequence that generates a given number of packets with the condition that members of the array of generated packets will have random data widths up to 128-bits. However, I noticed that the test picks one data-width option from the provided list and applies it to all generated packets. I want to make the data-widths non-uniform. Here are excerpts from my sequence item and the sequence.

//sequence item
.
.
rand bit [127:0] data[][];
rand int              data_width;
constraint data_width_c {
    foreach(data[i,j]) {
      data_width inside {8, 16, 32, 64, 128};
      
      if (data_width==8)    data[i][j][127:8]   == 0;
      if (data_width==16)   data[i][j][127:16]  == 0;
      if (data_width==32)   data[i][j][127:32]  == 0;
      if (data_width==64)   data[i][j][127:64]  == 0;
    }
  }
......

//========sequence body =============
......
  virtual task body();
    `uvm_do_with(pkt, { data_size == local::num_of_packets; foreach(data[idx1, idx2]){data_width dist {8 := 20, 16 := 20, 32 := 20, 64 := 20, 128 := 20};} });

  endtask : body
2

A couple of problems with your constraints as you have shown them. You never size the dynamic array data, so the foreach loop never iterates. The data_width constraint should be outside the loop.

Can you please explain what you mean by “I want to make the data-widths non-uniform” perhaps explain with an example set of values you are looking for.

3

Thank you, @dave_59 . What I meant is that the generated array of packets should contain packets of various sizes.

Currently, the sequence generates packets only 16-bit packets. e.g {…1BA6, 494F, 4CCA, 812C,…}

What I’m trying to achieve is as follows:
Example: array_of_packets = {X-bit-data, Y-bit-data, Z-bit-data, A-bit-data,…}. Where X, Y, Z, and A are 8, 16, 32 and 64. The order does not matter.

Same example using numbers: array_of_packets = {…, 6C, 2F7B, 18DA_012F, 7F2B_9A15_ACA3_F97E, …}

4

like Dave mentioned you need to consider to move
data_width inside {8, 16, 32, 64, 128}; outside of the loop.
then use solve … before to get data_width constraint before data constraint

5

You must be very concise about which variables you are randomizing. You just added a new variable named array_of_packets that hasn’t been mentioned before. And nothing you’ve shown so far has indicated how the values get limited to 16-bits.

Please provide a complete example with the exact declarations and how you intend to populate those variables using legal SystemVerilog syntax.