Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
About the UVM category	0	1294	January 1, 2023
UVM_SEQ_ARB_WEIGHTED Arbitration: How Does It Work and When Should It Be Used? UVM	1	11	June 8, 2026
Why does UVM need both wait_for_grant() and wait_for_item_done()? UVM	3	32	June 8, 2026
UVM Sequencer Arbitration: Is Sequence Priority Used During Queue Insertion or During Grant Selection? UVM	3	17	June 8, 2026
Understand the Difference between UVM_SEQ_ARB_FIFO and UVM_SEQ_ARB_STRICT_FIFO	3	25	June 5, 2026
Use of lock() method	1	12	June 5, 2026
For understanding factory usage UVM , set_type_override , factory , Polymorhphism	6	1607	June 3, 2026
Why Is Scoreboard Kept Separate from Agent in UVM? UVM	2	50	June 3, 2026
Understanding the Real Difference Between uvm_resource_db and uvm_config_db UVM	2	30	June 2, 2026
Why Did UVM Creators Make Separate Classes for uvm_transaction and uvm_sequence_item? UVM	1	40	May 26, 2026
Confusion About uvm_void in UVM Hierarchy UVM	3	47	May 26, 2026
Use case of uvm_void	1	32	May 26, 2026
Creating virtual function to get 'uvm_analysis_export' handles	2	58	May 8, 2026
P_sequencer and m_sequencer UVM	13	56192	April 28, 2026
Difference of reset/configure/main/shutdown phases and run phase UVM , UVM_PHASE , phase , UVM-phases , run_phase , uvm-run_phase , main_phase , run_phase-main_phase	5	123	April 20, 2026
Crash after Connecting SC proxy UVMC-Compilation	2	31	April 15, 2026
I need to know how many UVM active/Passive agents are required UVM	4	101	April 4, 2026
User-defined verbosity using uvm_config_db	3	83	March 30, 2026
Choosing between TLM get v/s peek tlm , uvm_blocking_peek_imp , uvm_blocking_get_imp , get-vs-peek	1	92	March 22, 2026
Bug (?) in uvm_pool SystemVerilog , UVM , uvm_event_pool	0	60	March 13, 2026
Back door access for uvm_mem UVM	3	1500	March 13, 2026
UVM Verification of I2C Slave IP with APB Registers UVM , Coverage , System-Verilog , SVA	2	112	March 10, 2026
Ensuring specific uvm_config_db::set always wins UVM , uvm_config_db	0	86	February 24, 2026
Configuring agent in Active / Passive mode uvm_config_db , activepassive-agent-configuration , uvm_agent , uvm_active_passive_enum	5	174	February 22, 2026
Bind interface for internal DUT forcing UVM	20	5584	February 21, 2026
Automation of creating different parameter sets combinations IP-Parameter	1	51	February 18, 2026
How to create a SystemVerilog testbench for my ALU's parent circuit? SystemVerilog , UVM	2	94	February 18, 2026
Connection from monitor to driver in reactive agent	1	61	February 16, 2026
P_sequencer / m_sequencer UVM	11	37063	February 13, 2026
UVM scoreboard interview question UVM , UVM-scoreboard	4	675	February 12, 2026