Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
About the UVM category	0	566	January 1, 2023
Default arguments for constructor	1	7	August 31, 2024
Compoent1 data to component 2's sequence UVM , tlm , uvm_tlm_analysis_fifo	3	11	August 30, 2024
Virtual sequence	4	31	August 30, 2024
Assign value to an enum from command line SystemVerilog , UVM , Command-Line-Processing , enum	2	21	August 30, 2024
Monitor sampling issues	2	32	August 29, 2024
Overriding a component having imps by a component which redefines the imps	1	19	August 28, 2024
How to override multiple instances of a base class with derived classes in one run? factory-overrides	4	57	August 28, 2024
Calling super.run_phase from and extended-extended test, but just want base test.run_phase	4	35	August 27, 2024
Data width is 128 bits but only LSB 32-bits are valid UVM , AMBA-AXI	8	1995	August 27, 2024
New function instead of create method SystemVerilog , UVM	3	44	August 26, 2024
Randomizing an array of transactions UVM , randomization-error , illegal-contraints	7	5359	August 24, 2024
Problem generating "uvm_dpi.dll" for UVM1.2 for QuestaSim 10.2c in 64 bit Windows UVM , Compile-UVM-12-in-Windos-64-bit	14	13423	August 23, 2024
Getting Warning VSIM-7076 and Fatal (Vsim -7019) while compiling UVM-1.2 package examples in questasim 10.6c on windows11 UVM	3	27	August 23, 2024
Accessing sequencer from a Sequence UVM	11	4284	August 23, 2024
Factory print does not show override override	3	40	August 22, 2024
Testing of Read/Write register through RAL when bug is there UVM , RAL	1	40	August 22, 2024
Agent instance becoming null during runtime UVM , uvm-uvm_config_db , config	1	39	August 21, 2024
# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq uvm-ral	1	32	August 21, 2024
Setting array of interfaces to UVM config database UVM	7	9026	August 20, 2024
Usage of config DB(Highest write wins)	1	63	August 17, 2024
Query on uvm_reg_hw_reset_seq RAL-UVM	1	44	August 19, 2024
Drive signal in the driver SystemVerilog	2	52	August 18, 2024
How to coordinate TB with 2 Drivers	0	40	August 16, 2024
Regarding set_timeout UVM , uvm_root , set_timeout	1	56	August 13, 2024
With help from Uvm_config_db can we set in lower Hierarchy(Ex -Agent) and get values in Upper Hierarchy(Ex-Env) UVM	6	965	August 13, 2024
What can be the harm in constructing analysis_port in new function of monitor?	1	47	August 12, 2024
Can we extend sequencer and driver from uvm_component?	5	91	August 12, 2024
How seq_item_port/export (Driver/Sequencer) are different from analysis ports? UVM	6	3866	August 12, 2024
Do we need get_full_name() in sequence item creation? If so, why? UVM , uvm_sequence , UVM_CREATE-UVM_SEQUENCE , get_full_name , uvm_sequence-body	3	1264	August 8, 2024