Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
About the UVM category	0	1147	January 1, 2023
VIP based verification	2	35	November 27, 2025
AHB Protocol: Data & Address Phase AHB	0	16	November 25, 2025
Uvm_hdl_read gives Incorrect value	1	35	November 23, 2025
Display uvm_info including ps values	7	32	November 23, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? OVM , SystemVerilog , UVM , Coverage	0	26	November 17, 2025
Wait_for_state() in a static module doesn't work as expected UVM-phase-methods , UVM_PHASE , phase , Cookbook-Phasing , UVM-phases , Related-to-UVM-phases , phasing , Phasing-within-a-static-entity	10	94	November 16, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses SystemVerilog , UVM , uvm-register-model	2	32	November 13, 2025
Individual field access causes extra reads/writes? SystemVerilog , UVM , uvm-register-model	5	30	November 12, 2025
UVM RAL: How to execute register access without updating mirrored value? UVM-RAL-UVM	1	48	November 8, 2025
Code debug help	2	68	November 5, 2025
Vertical re-use (from block to sub-system/chip level) UVM , reuse	5	3312	November 2, 2025
Migrating from IP to sub-system level	2	59	November 2, 2025
Why uvm_object_registry is called as lightweight proxy? UVM	1	47	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM	5	65	October 27, 2025
Question on use of RAL model for System-On-Chip verification	4	93	October 24, 2025
Multiple analysis ports to single implementation SystemVerilog , UVM , analysis-port	8	149	October 23, 2025
How to properly extend a test case from different parents SystemVerilog , UVM	2	103	October 21, 2025
How to deep copy UVM transaction containing queue of objects? SystemVerilog , UVM	3	56	October 21, 2025
How to use multiple sequences to override base test	14	180	October 17, 2025
Config db fatal isssue OVM , SystemVerilog , UVM	1	48	October 16, 2025
Clarification on sequence execution flow UVM cookbook figure	6	56	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction SystemVerilog , UVM	3	61	October 15, 2025
Getting the virtual interface in the test class or in the agent?	1	43	October 9, 2025
Protected registers behavior implementation with RAL UVM	1	56	October 8, 2025
Query on Register wr/rd verification by taking security state into consideration RAL	2	48	October 8, 2025
Write method as task	6	38	October 8, 2025
Updating UVM Component properties via Field Automation Macros apply_config_settings , field-macros , UVM-field-macros , superbuild_phase	7	62	October 8, 2025
Delay in update of mirrored value in explicit prediction RAL , prediction-monitor-scoreboard , RAL-UVM-PREDICTOR	7	50	October 8, 2025
Backdoor Read consumes simulation time RAL , UVM_BACKDOOR , uvm_ral	2	69	October 8, 2025