Can we print all TLM connections available in the test bench?

UVM
,
1

Hi,

Using the print_topology we can print the topoloy for the testbench which shows the tlm ports of the components also.
But is there any method where we can print the interconnection between the ports ? So that just like seeing the topology we can understand which prot is connected to which component.

2

Yes, for each port, you can find you what component it is connected to.

See

1 Like
3

Thanks for the solution.

4

Hi Dave,

This page is not found. Can you please check it out and make change?

Thanks.

5

Hi,

You could use get_connected_to and get_provided_to methods from that port.
See source: Port Base Classes Port Base Classes

Example:

class RefModel extends uvm_component;
  `uvm_component_utils(RefModel)

  // Input port
  `uvm_analysis_imp_decl(_ctrl_in_port)
  uvm_analysis_imp_ctrl_in_port#(ControlTrans, RefModel) ctrl_in_port;

  // Output port
  uvm_analysis_port #(DataTrans) data_out_port;

  function void end_of_elaboration_phase(uvm_phase phase);
    uvm_port_list list;

    this.ctrl_in_port.get_provided_to(list);
    if (list.size() == 0) begin
      `uvm_error(get_type_name(), $sformatf("%s.ctrl_in_port c to any uvm_analysis_port", this.get_full_name()));
    end
    else begin
      `uvm_info(get_type_name(), $sformatf("%s.ctrl_in_port is connected to d%0d uvm_analysis_port. Listed below:", this.get_full_name(), list.size()), UVM_HIGH)
      foreach(list[name]) begin
        `uvm_info(get_type_name(), $sformatf("- %s - %s", name, list[name].get_full_name()), UVM_HIGH)
      end
    end
  endfunction

  // Other lines: new, build_phase, etc.
endclass
6

link fixed