Can we print all TLM connections available in the test bench?

UVM
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1

Hi,

Using the print_topology we can print the topoloy for the testbench which shows the tlm ports of the components also.
But is there any method where we can print the interconnection between the ports ? So that just like seeing the topology we can understand which prot is connected to which component.

2

Yes, for each port, you can find you what component it is connected to.

See Debugging/BuiltInDebug | Verification Academy

3

Thanks for the solution.