Topics tagged UVM

Topic	Replies	Views	Activity
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	4	3268	October 30, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	29	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	30	October 27, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	107	October 23, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	63	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	37	October 21, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	30	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	50	October 15, 2025
Protected registers behavior implementation with RAL UVM UVM	1	49	October 8, 2025
Loop to randomize RAL fields across multiple registers SystemVerilog UVM	0	26	October 8, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	40	October 2, 2025
Facing error when passing arguments in the hierarchy when using $assertoff UVM UVM , assetions , assertoff	2	332	September 27, 2025
Project for self practice for creating TB UVM UVM	1	46	September 25, 2025
UVM INFO Message from SPELLCHK UVM UVM , UVM-UVM_INFO-uvm_spell_chkr	4	802	September 12, 2025
How to write scoreboard for in order and out of order transactions in AXI4 UVM UVM	1	226	September 12, 2025
Ral explicit prediction UVM UVM , RAL	1	52	September 9, 2025
[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block? UVM UVM , Backdoor-method	5	1401	September 4, 2025
P_sequencer and m_sequencer UVM UVM	12	55609	September 1, 2025
c-uvm synchronization without DPI UVM UVM , Synchronization , C , co-sim	15	167	August 26, 2025
Agent to agent communication UVM UVM	2	56	August 18, 2025
Fatal Error in Visualizer during post_simulation UVM SystemVerilog , UVM , Visualizer-Debug-Environment	2	43	July 18, 2025
What is meant by read-modify -write in register access generally? UVM UVM	5	3275	July 16, 2025
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	7	94	July 15, 2025
UVM Default and UVM ALL ON UVM UVM	2	134	July 7, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	62	July 2, 2025
Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts UVM UVM	1	126	July 2, 2025
Parameterized interface UVM UVM	3	162	June 30, 2025
TLM PORTS how it giving the access of other class TASK with other class handle UVM UVM	1	52	June 26, 2025
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM UVM , uvm_reg_bit_bash	5	2208	June 26, 2025
Why final phase is top to bottom? UVM UVM	1	79	June 25, 2025

Vertical re-use (from block to sub-system/chip level)

UVM

UVM , reuse

4

3268

October 30, 2025

Why uvm_object_registry is called as lightweight proxy?

UVM

1

29

October 28, 2025

UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure

UVM

5

30

October 27, 2025

Multiple analysis ports to single implementation

UVM

SystemVerilog , UVM , analysis-port

8

107

October 23, 2025

How to properly extend a test case from different parents

UVM

SystemVerilog , UVM

2

63

October 21, 2025

How to deep copy UVM transaction containing queue of objects?

UVM

SystemVerilog , UVM

3

37

October 21, 2025

Config db fatal isssue

UVM

OVM , SystemVerilog , UVM

1

30

October 16, 2025

Getting last transaction in consumer repetitively even though producer is sending all transaction

UVM

SystemVerilog , UVM

3

50

October 15, 2025

Protected registers behavior implementation with RAL

UVM

1

49

October 8, 2025

Loop to randomize RAL fields across multiple registers

SystemVerilog

UVM

0

26

October 8, 2025

How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times

UVM

6

40

October 2, 2025

Facing error when passing arguments in the hierarchy when using $assertoff

UVM

UVM , assetions , assertoff

2

332

September 27, 2025

Project for self practice for creating TB

UVM

1

46

September 25, 2025

UVM INFO Message from SPELLCHK

UVM

UVM , UVM-UVM_INFO-uvm_spell_chkr

4

802

September 12, 2025

How to write scoreboard for in order and out of order transactions in AXI4

UVM

1

226

September 12, 2025

Ral explicit prediction

UVM

UVM , RAL

1

52

September 9, 2025

[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block?

UVM

UVM , Backdoor-method

5

1401

September 4, 2025

P_sequencer and m_sequencer

UVM

12

55609

September 1, 2025

c-uvm synchronization without DPI

UVM

UVM , Synchronization , C , co-sim

15

167

August 26, 2025

Agent to agent communication

UVM

2

56

August 18, 2025

Fatal Error in Visualizer during post_simulation

UVM

SystemVerilog , UVM , Visualizer-Debug-Environment

2

43

July 18, 2025

What is meant by read-modify -write in register access generally?

UVM

5

3275

July 16, 2025

Coverage bins sampling an uninitialized virtual interface object

SystemVerilog

UVM , Coverage

7

94

July 15, 2025

UVM Default and UVM ALL ON

UVM

2

134

July 7, 2025

Why do compare need to arguments, specially why second arguments of uvm_comparer comparer

UVM

4

62

July 2, 2025

Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts

UVM

1

126

July 2, 2025

Parameterized interface

UVM

3

162

June 30, 2025

TLM PORTS how it giving the access of other class TASK with other class handle

UVM

1

52

June 26, 2025

Confusing UVM_ERROR in uvm_reg_bit_bash_seq

UVM

UVM , uvm_reg_bit_bash

5

2208

June 26, 2025

Why final phase is top to bottom?

UVM

1

79

June 25, 2025