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Vertical re-use (from block to sub-system/chip level)
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4
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3268
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October 30, 2025
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Why uvm_object_registry is called as lightweight proxy?
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1
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29
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October 28, 2025
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UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure
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5
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30
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October 27, 2025
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Multiple analysis ports to single implementation
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8
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107
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October 23, 2025
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How to properly extend a test case from different parents
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2
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63
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October 21, 2025
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How to deep copy UVM transaction containing queue of objects?
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3
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37
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October 21, 2025
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Config db fatal isssue
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1
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30
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October 16, 2025
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Getting last transaction in consumer repetitively even though producer is sending all transaction
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3
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50
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October 15, 2025
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Protected registers behavior implementation with RAL
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1
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49
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October 8, 2025
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Loop to randomize RAL fields across multiple registers
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0
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26
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October 8, 2025
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How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times
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6
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40
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October 2, 2025
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Facing error when passing arguments in the hierarchy when using $assertoff
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2
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332
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September 27, 2025
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Project for self practice for creating TB
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1
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46
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September 25, 2025
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UVM INFO Message from SPELLCHK
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4
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802
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September 12, 2025
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How to write scoreboard for in order and out of order transactions in AXI4
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1
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226
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September 12, 2025
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Ral explicit prediction
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1
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52
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September 9, 2025
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[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block?
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5
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1401
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September 4, 2025
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P_sequencer and m_sequencer
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12
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55609
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September 1, 2025
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c-uvm synchronization without DPI
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15
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167
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August 26, 2025
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Agent to agent communication
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2
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56
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August 18, 2025
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Fatal Error in Visualizer during post_simulation
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2
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43
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July 18, 2025
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What is meant by read-modify -write in register access generally?
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5
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3275
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July 16, 2025
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Coverage bins sampling an uninitialized virtual interface object
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7
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94
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July 15, 2025
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UVM Default and UVM ALL ON
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2
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134
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July 7, 2025
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Why do compare need to arguments, specially why second arguments of uvm_comparer comparer
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4
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62
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July 2, 2025
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Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts
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1
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126
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July 2, 2025
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Parameterized interface
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3
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162
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June 30, 2025
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TLM PORTS how it giving the access of other class TASK with other class handle
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1
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52
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June 26, 2025
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Confusing UVM_ERROR in uvm_reg_bit_bash_seq
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5
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2208
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June 26, 2025
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Why final phase is top to bottom?
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1
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79
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June 25, 2025
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