Topics tagged UVM

Topic	Replies	Views	Activity
c-uvm synchronization without DPI UVM UVM , Synchronization , C , co-sim	13	63	August 22, 2025
Agent to agent communication UVM UVM	2	25	August 18, 2025
Fatal Error in Visualizer during post_simulation UVM SystemVerilog , UVM , Visualizer-Debug-Environment	2	34	July 18, 2025
What is meant by read-modify -write in register access generally? UVM UVM	5	3248	July 16, 2025
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	7	69	July 15, 2025
UVM Default and UVM ALL ON UVM UVM	2	95	July 7, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	52	July 2, 2025
Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts UVM UVM	1	95	July 2, 2025
Parameterized interface UVM UVM	3	147	June 30, 2025
TLM PORTS how it giving the access of other class TASK with other class handle UVM UVM	1	44	June 26, 2025
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM UVM , uvm_reg_bit_bash	5	2191	June 26, 2025
Why final phase is top to bottom? UVM UVM	1	57	June 25, 2025
UVM_FATAL @ 0: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq UVM UVM	2	41	June 23, 2025
Reference model UVM SystemVerilog , UVM	1	58	June 21, 2025
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	26	20430	June 18, 2025
RAL set() method followed by update() method modify all 32 bits of a 32 bit register! UVM UVM , RAL	1	36	June 18, 2025
Can anyone help to write assertion for 200MHz clk check? UVM UVM , assertion	3	175	June 14, 2025
Raise_objection in uvm_sequence class UVM UVM , sequence-raise-and-drop-phase	15	6067	June 13, 2025
Uvm_phase : build_phase UVM UVM	6	94	June 12, 2025
Functional Coverage At Subsystem or SOC Level SystemVerilog UVM , code-coverage , SystemVerilog-FunctionalCoverage	2	106	June 10, 2025
Overiding the soft constraints and that variable should not get randomized further when its called to randomize UVM UVM , constraint-randomization , randomization , constraints	1	85	June 6, 2025
UVM Simulation is not ending UVM SystemVerilog , UVM	7	107	June 6, 2025
How is deep copy and shallow copy executed in clone[create+copy] method together? UVM UVM , deep-copy-and-shallow-copy , Copy , clone	4	6823	June 5, 2025
PCIe Question about LCRC and ECRC! SystemVerilog SystemVerilog , UVM , PCIe , PCIe-Gen-5 , pcie-protocol-explanation	1	84	May 30, 2025
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	22	11496	May 29, 2025
First Step in Design Verification UVM UVM , Verification , Formal-Verification , RAL-UVM	2	107	May 27, 2025
How RAL knows automatically when ever DUT status registers changes UVM UVM	2	823	May 20, 2025
How to separate the namespace between a random-constrained object's member and the calling class' member SystemVerilog UVM	6	40	May 20, 2025
Functional Coverage for larger bit size SystemVerilog UVM , Coverage	1	55	May 17, 2025
UVM tlm port to multiple implementation port connection UVM UVM , tlm	0	30	May 14, 2025