Topics tagged UVM

Topic	Replies	Views	Activity
Access register/field value in DUT without acquiring the XatomicX semaphore UVM UVM , Systemverilog-UVM-RAL	0	38	September 25, 2024
I want to detect glitch for glitch mux UVM UVM	2	37	October 3, 2024
How to override uvm_config_db from extended class? UVM UVM , A-agent_configuration-object-provided-to-constructor-is-not-valid-for-class-agent-Update-the-configuration-based-on-prior-Warning-messages	7	4253	October 3, 2024
Uvm transaction class related UVM UVM	3	48	October 2, 2024
Data width is 128 bits but only LSB 32-bits are valid UVM UVM , AMBA-AXI	11	2102	October 2, 2024
Constraint to randomize elements of an array such that at least one is a multiple of 4 UVM UVM , constraint-randomization , systemverilog-arrays-struct-constraint-randomization-indexes	5	539	September 30, 2024
Disable uvm_reg_field.svh warnings UVM UVM , -UVM-warnings-disable	5	656	September 26, 2024
How to write scoreboard for in order and out of order transactions in AXI4 UVM UVM	0	58	September 26, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	82	September 26, 2024
Printing topology in top module UVM UVM	13	10235	September 19, 2024
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	43	September 19, 2024
Suggestions for +uvm_set_verbosity UVM UVM , uvm_set_verbosity	5	90	September 18, 2024
How to disable super.body in derived sequences from test for some sequences in uvm UVM UVM	3	73	September 16, 2024
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	22	19080	September 13, 2024
How can I create an array of agents of same type? UVM UVM , array-of-UVM-agents	11	1104	September 12, 2024
Agent instance becoming null during runtime UVM UVM , uvm-uvm_config_db , config	2	95	September 10, 2024
Tlm analysis FIFO/uvm analysis port connection problem UVM UVM , UVM-TLM-Analysis-port , systemverilog-uvm	9	2254	September 7, 2024
I encounter UVM_WARININGs for race condition while doing register set/writes UVM UVM	1	58	September 5, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	80	September 3, 2024
Compoent1 data to component 2's sequence UVM UVM , tlm , uvm_tlm_analysis_fifo	3	69	August 30, 2024
Assign value to an enum from command line UVM SystemVerilog , UVM , Command-Line-Processing , enum	2	104	August 30, 2024
Facing issue while integrating 2 VIP's SystemVerilog UVM	0	69	August 27, 2024
New function instead of create method UVM SystemVerilog , UVM	3	131	August 26, 2024
Randomizing an array of transactions UVM UVM , randomization-error , illegal-contraints	7	5429	August 24, 2024
Problem generating "uvm_dpi.dll" for UVM1.2 for QuestaSim 10.2c in 64 bit Windows UVM UVM , Compile-UVM-12-in-Windos-64-bit	14	13508	August 23, 2024
Getting Warning VSIM-7076 and Fatal (Vsim -7019) while compiling UVM-1.2 package examples in questasim 10.6c on windows11 UVM UVM	3	57	August 23, 2024
Accessing sequencer from a Sequence UVM UVM	11	4391	August 23, 2024
Testing of Read/Write register through RAL when bug is there UVM UVM , RAL	1	94	August 22, 2024
Setting array of interfaces to UVM config database UVM UVM	7	9098	August 20, 2024
Regarding set_timeout UVM UVM , uvm_root , set_timeout	1	106	August 13, 2024