Topics tagged UVM

Topic	Replies	Views	Activity
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	38	December 19, 2024
How can we Make reuseable testbench architecture In AXI4? UVM UVM	1	26	December 17, 2024
Coverpoint bins for fractional values SystemVerilog UVM , Coverage	4	42	December 14, 2024
Why testcase passing in VCS simulator and Failing in Cadence simulator for the same code UVM SystemVerilog , UVM	1	32	December 13, 2024
Error casting p_sequencer UVM UVM , casting-p_sequencer	2	2893	December 9, 2024
Why we should use non-blocking assignments in driver and blocking assignments in monitor? UVM UVM	15	10407	December 8, 2024
Reference code for Out of Order pipelined driver UVM UVM , Cookbook-DriverUse-Models	2	1631	December 4, 2024
Randc VS Unique SystemVerilog SystemVerilog , UVM , constraint-randomization	1	63	December 1, 2024
Why Override the Default Sequence for Reactive Slaves in UVM? UVM UVM	4	45	November 28, 2024
Regarding UVM_QUEUE and their methods UVM OVM , SystemVerilog , UVM	2	55	November 25, 2024
Driver will ask to sequence to do randomization in uvm UVM UVM	1	39	November 22, 2024
Coverage in Monitor UVM UVM	2	39	November 17, 2024
Best practice to align interfaces in UVM testbench UVM UVM	6	60	November 14, 2024
Calling of build phase? UVM UVM , UVM_PHASE , build_phase	26	20025	November 14, 2024
Difference between get_next_item and get? UVM UVM	8	5391	November 14, 2024
After removing get_response () I am not seeing the second transaction initiated by master UVM UVM	7	61	November 12, 2024
UVM TB interview question UVM UVM	2	456	November 8, 2024
Is there a UVM Connect version that is compatible with UVM 1800.2-2020? UVM UVM , uvm-connect , UVMConnect , UVMC , Cookbook-UVM-Connect	6	1137	November 7, 2024
What data type to use in uvm_config_db for an queue of class_object UVM UVM	2	1948	June 6, 2013
How to read UVM_TESTNAME using uvm_config_db UVM UVM	5	64	November 1, 2024
Has anyone implemented a Write 1 only self-clearing policy for a uvm_reg_field? UVM UVM , uvm_reg , Access-Policy	2	40	October 30, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	2	91	October 27, 2024
VIP development UVM UVM	6	1801	October 22, 2024
Uvm transaction class related UVM UVM	4	96	October 21, 2024
Uvm factory registration disambiguation UVM UVM , uvm-factory-disambiguation-registration	7	668	October 20, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	90	October 18, 2024
Constraint to randomize elements of an array such that at least one is a multiple of 4 UVM UVM , constraint-randomization , systemverilog-arrays-struct-constraint-randomization-indexes	12	706	October 16, 2024
I need to generate HEX File depending on the random parameter passed from the test sequence and also how to preload DUT memory UVM SystemVerilog , UVM	1	45	October 15, 2024
I want to use DPI-C with package SystemVerilog SystemVerilog , UVM , dpi-c	3	56	October 11, 2024
UVM1.2 : uvm_traversal.svh giving uvm_component name constraint warning UVM UVM , uvm_warning , UVM-12	15	4137	October 9, 2024

Implementing Outstanding AXI transactions using RAL

UVM

UVM , RAL , uvm-ral

1

38

December 19, 2024

How can we Make reuseable testbench architecture In AXI4?

UVM

1

26

December 17, 2024

Coverpoint bins for fractional values

SystemVerilog

UVM , Coverage

4

42

December 14, 2024

Why testcase passing in VCS simulator and Failing in Cadence simulator for the same code

UVM

SystemVerilog , UVM

1

32

December 13, 2024

Error casting p_sequencer

UVM

UVM , casting-p_sequencer

2

2893

December 9, 2024

Why we should use non-blocking assignments in driver and blocking assignments in monitor?

UVM

15

10407

December 8, 2024

Reference code for Out of Order pipelined driver

UVM

UVM , Cookbook-DriverUse-Models

2

1631

December 4, 2024

Randc VS Unique

SystemVerilog

SystemVerilog , UVM , constraint-randomization

1

63

December 1, 2024

Why Override the Default Sequence for Reactive Slaves in UVM?

UVM

4

45

November 28, 2024

Regarding UVM_QUEUE and their methods

UVM

OVM , SystemVerilog , UVM

2

55

November 25, 2024

Driver will ask to sequence to do randomization in uvm

UVM

1

39

November 22, 2024

Coverage in Monitor

UVM

2

39

November 17, 2024

Best practice to align interfaces in UVM testbench

UVM

6

60

November 14, 2024

Calling of build phase?

UVM

UVM , UVM_PHASE , build_phase

26

20025

November 14, 2024

Difference between get_next_item and get?

UVM

8

5391

November 14, 2024

After removing get_response () I am not seeing the second transaction initiated by master

UVM

7

61

November 12, 2024

UVM TB interview question

UVM

2

456

November 8, 2024

Is there a UVM Connect version that is compatible with UVM 1800.2-2020?

UVM

UVM , uvm-connect , UVMConnect , UVMC , Cookbook-UVM-Connect

6

1137

November 7, 2024

What data type to use in uvm_config_db for an queue of class_object

UVM

2

1948

June 6, 2013

How to read UVM_TESTNAME using uvm_config_db

UVM

5

64

November 1, 2024

Has anyone implemented a Write 1 only self-clearing policy for a uvm_reg_field?

UVM

UVM , uvm_reg , Access-Policy

2

40

October 30, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

2

91

October 27, 2024

VIP development

UVM

6

1801

October 22, 2024

Uvm transaction class related

UVM

4

96

October 21, 2024

Uvm factory registration disambiguation

UVM

UVM , uvm-factory-disambiguation-registration

7

668

October 20, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog