Topics tagged UVM

Topic	Replies	Views	Activity
VIP development UVM UVM	6	1752	October 22, 2024
Uvm transaction class related UVM UVM	4	72	October 21, 2024
Uvm factory registration disambiguation UVM UVM , uvm-factory-disambiguation-registration	7	650	October 20, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	1	27	October 20, 2024
RESET Assertion with out clock dependency SystemVerilog OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog	1	40	October 18, 2024
Constraint to randomize elements of an array such that at least one is a multiple of 4 UVM UVM , constraint-randomization , systemverilog-arrays-struct-constraint-randomization-indexes	12	625	October 16, 2024
I need to generate HEX File depending on the random parameter passed from the test sequence and also how to preload DUT memory UVM SystemVerilog , UVM	1	40	October 15, 2024
I want to use DPI-C with package SystemVerilog SystemVerilog , UVM , dpi-c	3	39	October 11, 2024
UVM1.2 : uvm_traversal.svh giving uvm_component name constraint warning UVM UVM , uvm_warning , UVM-12	15	4121	October 9, 2024
Access register/field value in DUT without acquiring the XatomicX semaphore UVM UVM , Systemverilog-UVM-RAL	0	56	September 25, 2024
I want to detect glitch for glitch mux UVM UVM	2	78	October 3, 2024
How to override uvm_config_db from extended class? UVM UVM , A-agent_configuration-object-provided-to-constructor-is-not-valid-for-class-agent-Update-the-configuration-based-on-prior-Warning-messages	7	4288	October 3, 2024
Data width is 128 bits but only LSB 32-bits are valid UVM UVM , AMBA-AXI	11	2136	October 2, 2024
Disable uvm_reg_field.svh warnings UVM UVM , -UVM-warnings-disable	5	679	September 26, 2024
How to write scoreboard for in order and out of order transactions in AXI4 UVM UVM	0	83	September 26, 2024
Handling multiple RAL request simultaneously UVM UVM , RAL	2	105	September 26, 2024
Printing topology in top module UVM UVM	13	10282	September 19, 2024
How to Selectively skip STS ( RO ) registers in bit_bash UVM UVM , RAL , uvm_reg_bit_bash	0	60	September 19, 2024
Suggestions for +uvm_set_verbosity UVM UVM , uvm_set_verbosity	5	101	September 18, 2024
How to disable super.body in derived sequences from test for some sequences in uvm UVM UVM	3	86	September 16, 2024
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	22	19155	September 13, 2024
How can I create an array of agents of same type? UVM UVM , array-of-UVM-agents	11	1141	September 12, 2024
Agent instance becoming null during runtime UVM UVM , uvm-uvm_config_db , config	2	105	September 10, 2024
Tlm analysis FIFO/uvm analysis port connection problem UVM UVM , UVM-TLM-Analysis-port , systemverilog-uvm	9	2285	September 7, 2024
I encounter UVM_WARININGs for race condition while doing register set/writes UVM UVM	1	62	September 5, 2024
How to check the register is implemented in UVM RAL with the address UVM UVM , RAL , uvm_reg	1	96	September 3, 2024
Compoent1 data to component 2's sequence UVM UVM , tlm , uvm_tlm_analysis_fifo	3	80	August 30, 2024
Assign value to an enum from command line UVM SystemVerilog , UVM , Command-Line-Processing , enum	2	116	August 30, 2024
Facing issue while integrating 2 VIP's SystemVerilog UVM	0	79	August 27, 2024
New function instead of create method UVM SystemVerilog , UVM	3	140	August 26, 2024

VIP development

UVM

6

1752

October 22, 2024

Uvm transaction class related

UVM

4

72

October 21, 2024

Uvm factory registration disambiguation

UVM

UVM , uvm-factory-disambiguation-registration

7

650

October 20, 2024

Advantage of calling set() over write()

UVM

UVM , RAL , uvm-ral

1

27

October 20, 2024

RESET Assertion with out clock dependency

SystemVerilog

OVM , SystemVerilog , Announcements , UVM , assertion , RAL , SVA , system-verilog-assertion-SVA , Assertion-Based-Verification , constraint-randomization , assert-property , Assertion-system-verilog