Topics tagged UVM

Topic	Replies	Views	Activity
Coverage bins sampling an uninitialized virtual interface object SystemVerilog UVM , Coverage	1	16	July 10, 2025
UVM Default and UVM ALL ON UVM UVM	2	63	July 7, 2025
Why do compare need to arguments, specially why second arguments of uvm_comparer comparer UVM UVM	4	38	July 2, 2025
Difference Between `uvm_config_db` and `uvm_resource_db` in Non-Component Contexts UVM UVM	1	52	July 2, 2025
Parameterized interface UVM UVM	3	127	June 30, 2025
TLM PORTS how it giving the access of other class TASK with other class handle UVM UVM	1	35	June 26, 2025
Confusing UVM_ERROR in uvm_reg_bit_bash_seq UVM UVM , uvm_reg_bit_bash	5	2177	June 26, 2025
Why final phase is top to bottom? UVM UVM	1	38	June 25, 2025
UVM_FATAL @ 0: reporter@@seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in seq UVM UVM	2	35	June 23, 2025
Reference model UVM SystemVerilog , UVM	1	45	June 21, 2025
Interview Questions on Assertions SystemVerilog SystemVerilog , UVM	26	20201	June 18, 2025
RAL set() method followed by update() method modify all 32 bits of a 32 bit register! UVM UVM , RAL	1	26	June 18, 2025
Can anyone help to write assertion for 200MHz clk check? UVM UVM , assertion	3	134	June 14, 2025
Raise_objection in uvm_sequence class UVM UVM , sequence-raise-and-drop-phase	15	5981	June 13, 2025
Uvm_phase : build_phase UVM UVM	6	85	June 12, 2025
Functional Coverage At Subsystem or SOC Level SystemVerilog UVM , code-coverage , SystemVerilog-FunctionalCoverage	2	84	June 10, 2025
Overiding the soft constraints and that variable should not get randomized further when its called to randomize UVM UVM , constraint-randomization , randomization , constraints	1	62	June 6, 2025
UVM Simulation is not ending UVM SystemVerilog , UVM	7	81	June 6, 2025
How is deep copy and shallow copy executed in clone[create+copy] method together? UVM UVM , deep-copy-and-shallow-copy , Copy , clone	4	6799	June 5, 2025
PCIe Question about LCRC and ECRC! SystemVerilog SystemVerilog , UVM , PCIe , PCIe-Gen-5 , pcie-protocol-explanation	1	54	May 30, 2025
How can we verify a memory whose address location is swapped UVM UVM , memory-verification	22	11451	May 29, 2025
First Step in Design Verification UVM UVM , Verification , Formal-Verification , RAL-UVM	2	84	May 27, 2025
How RAL knows automatically when ever DUT status registers changes UVM UVM	2	816	May 20, 2025
How to separate the namespace between a random-constrained object's member and the calling class' member SystemVerilog UVM	6	38	May 20, 2025
Functional Coverage for larger bit size SystemVerilog UVM , Coverage	1	49	May 17, 2025
UVM tlm port to multiple implementation port connection UVM UVM , tlm	0	27	May 14, 2025
Using callbacks to change access to control fields within the same register UVM UVM , RAL , UVM-callback	1	38	May 12, 2025
Reset code in uvm UVM UVM , reset	3	87	May 12, 2025
Regarding get_next_item implementation in uvm_sequencer base class UVM UVM	11	591	May 12, 2025
Hierarchical reference from package not allowed UVM SystemVerilog , UVM , Package	9	66	May 11, 2025