Topics tagged UVM

Topic	Replies	Views	Activity
Calling a Task at the end of run_phase UVM UVM , UVM-phases	3	80	January 17, 2026
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	2	611	January 7, 2026
Working of uvm_cmdline_processor::get_arg_matches UVM UVM , uvm_cmdline_processor , get_arg_matches	3	58	January 6, 2026
Assertion error SystemVerilog SystemVerilog , UVM , assertion , SVA	3	49	January 5, 2026
Confusion with the master monitor and slave monitor functionality UVM UVM , SPI-Test-Plan	3	92	December 22, 2025
UVM 1.2 new warning - a resource with meta characters in the field name has been created UVM UVM , uvm_reg_block , Resource_db , UVMRSRCNOREGEX , UVM-12 , uvm-warning	12	7317	December 18, 2025
Significance of 'contxt' Argument for create() functions of uvm_component_registry N uvm_object_registry UVM UVM , Significance-of-contxt-Argument-for-create-functions-of-uvm_component_registry-N-uvm_object_registry	2	1164	December 6, 2025
What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules? UVM OVM , SystemVerilog , UVM , Coverage	0	75	November 17, 2025
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	76	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	48	November 12, 2025
Vertical re-use (from block to sub-system/chip level) UVM UVM , reuse	5	3360	November 2, 2025
Why uvm_object_registry is called as lightweight proxy? UVM UVM	1	71	October 28, 2025
UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure UVM UVM	5	110	October 27, 2025
Multiple analysis ports to single implementation UVM SystemVerilog , UVM , analysis-port	8	216	October 23, 2025
How to properly extend a test case from different parents UVM SystemVerilog , UVM	2	139	October 21, 2025
How to deep copy UVM transaction containing queue of objects? UVM SystemVerilog , UVM	3	95	October 21, 2025
Config db fatal isssue UVM OVM , SystemVerilog , UVM	1	87	October 16, 2025
Getting last transaction in consumer repetitively even though producer is sending all transaction UVM SystemVerilog , UVM	3	87	October 15, 2025
Protected registers behavior implementation with RAL UVM UVM	1	73	October 8, 2025
Loop to randomize RAL fields across multiple registers SystemVerilog UVM	0	41	October 8, 2025
How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times UVM UVM	6	70	October 2, 2025
Facing error when passing arguments in the hierarchy when using $assertoff UVM UVM , assetions , assertoff	2	356	September 27, 2025
Project for self practice for creating TB UVM UVM	1	75	September 25, 2025
UVM INFO Message from SPELLCHK UVM UVM , UVM-UVM_INFO-uvm_spell_chkr	4	874	September 12, 2025
How to write scoreboard for in order and out of order transactions in AXI4 UVM UVM	1	258	September 12, 2025
Ral explicit prediction UVM UVM , RAL	1	83	September 9, 2025
[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block? UVM UVM , Backdoor-method	5	1426	September 4, 2025
P_sequencer and m_sequencer UVM UVM	12	55874	September 1, 2025
c-uvm synchronization without DPI UVM UVM , Synchronization , C , co-sim	15	227	August 26, 2025
Agent to agent communication UVM UVM	2	82	August 18, 2025