Topics tagged UVM

Topic	Replies	Views	Activity
Correct way to kill sequences UVM UVM , stop_seqeunces	9	6720	July 26, 2024
Uvm_path_e vs uvm_door_e UVM SystemVerilog , UVM , uvm-ral	2	8	July 26, 2024
Sequence Stop or Kill UVM SystemVerilog , UVM	2	13	July 26, 2024
Phase raise and drop objection UVM SystemVerilog , UVM	4	21	July 26, 2024
Suggestions for uvm_phase API UVM UVM , UVM_PHASE	1	15	July 25, 2024
Using the string I provided in the create function UVM SystemVerilog , UVM	2	18	July 25, 2024
Analysis Export and Fifo in an uvm_object? UVM UVM , uvm_object , uvm_tlm_analysis_fifo , analysis-export	7	1813	July 24, 2024
Override by type with name conflicts UVM UVM , factory , set_type_override_by_type , factory-overrides , uvm-factory , uvm-factory-override	1	49	July 24, 2024
What is the difference between uvm_config_db and uvm_resource_db? UVM UVM , uvm_config	17	41756	July 23, 2024
Why is it invalid to connect a single blocking_put_port to multiple imps? UVM UVM	2	26	July 23, 2024
Why UVM allows connecting multiple exports/imps to a single put port UVM UVM , export-and-port , UVM-TLM-Port_Export	1	457	July 23, 2024
Uvm_event ordering UVM SystemVerilog , UVM	1	37	July 21, 2024
How do export "DPI-C" task call sequence? UVM UVM	10	3879	July 19, 2024
Can anyone please me to generate below constraint SystemVerilog UVM	1	65	July 17, 2024
Cell 'xxx' cannot be found in liblist for binding instance 'xxx' UVM UVM	2	33	July 17, 2024
How to use tlm_analysis_fifo? UVM UVM	14	18218	July 17, 2024
Connecting scoreboard with more than one monitor UVM UVM , UVM-scoreboard	6	83	July 17, 2024
Thousands of prints to log: 'run' phase is ready to proceed to the 'extract' phase UVM UVM , uvm_objection , TEST_DONE	6	1723	July 16, 2024
TLM port for many to 1 connection UVM UVM	1	78	July 15, 2024
Two Clock in Clocking block UVM UVM , Clocking-Block	16	930	July 10, 2024
How to connect scoreboard with more than one monitor UVM UVM , monitor , UVM-scoreboard	6	10487	July 10, 2024
Uvm_comparer::compare_field_int error UVM UVM	6	66	July 8, 2024
Different RESET Type on UVM register model UVM UVM , RAL-UVM	5	1728	July 3, 2024
Uvm_field__ macro for multi dimensional dynamic array UVM UVM , multi-dimensional-dynamic-array , uvm_field_macro	1	634	July 8, 2022
AHB Lite protocol Verification UVM SystemVerilog , UVM , Coverage , assertion	1	92	July 5, 2024
What happens to threads that don't finish UVM UVM , System-Verilog , for-loop-fork-join_none , FIFO-UVM-ConstrainedRandom	4	372	July 4, 2024
Coverage class port declaration Coverage UVM	1	45	July 2, 2024
Regarding hdl path for UVM RAL UVM UVM , Backdoor_access-HDL-access-methods	9	4334	July 1, 2024
UVM factory registration UVM UVM , UVM-Factory-Registration	8	4751	June 28, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM UVM , uvm-ral , Ral-write-and-read-methhods	4	3145	June 28, 2024