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Calling a Task at the end of run_phase
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3
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76
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January 17, 2026
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AHB Lite protocol Verification
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2
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608
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January 7, 2026
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Working of uvm_cmdline_processor::get_arg_matches
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3
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56
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January 6, 2026
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Assertion error
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3
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48
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January 5, 2026
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Confusion with the master monitor and slave monitor functionality
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3
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91
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December 22, 2025
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UVM 1.2 new warning - a resource with meta characters in the field name has been created
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12
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7315
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December 18, 2025
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Significance of 'contxt' Argument for create() functions of uvm_component_registry N uvm_object_registry
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2
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1163
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December 6, 2025
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What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
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0
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73
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November 17, 2025
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UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses
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2
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74
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November 13, 2025
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Individual field access causes extra reads/writes?
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5
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48
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November 12, 2025
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Vertical re-use (from block to sub-system/chip level)
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5
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3356
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November 2, 2025
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Why uvm_object_registry is called as lightweight proxy?
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1
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69
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October 28, 2025
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UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure
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5
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110
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October 27, 2025
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Multiple analysis ports to single implementation
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8
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214
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October 23, 2025
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How to properly extend a test case from different parents
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2
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138
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October 21, 2025
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How to deep copy UVM transaction containing queue of objects?
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3
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94
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October 21, 2025
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Config db fatal isssue
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1
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85
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October 16, 2025
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Getting last transaction in consumer repetitively even though producer is sending all transaction
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3
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87
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October 15, 2025
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Protected registers behavior implementation with RAL
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1
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73
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October 8, 2025
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Loop to randomize RAL fields across multiple registers
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0
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41
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October 8, 2025
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How to find the functional coverage of a signal which is declared in a module. This module is instantiated 256 times
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6
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67
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October 2, 2025
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Facing error when passing arguments in the hierarchy when using $assertoff
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2
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355
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September 27, 2025
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Project for self practice for creating TB
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1
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74
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September 25, 2025
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UVM INFO Message from SPELLCHK
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4
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873
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September 12, 2025
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How to write scoreboard for in order and out of order transactions in AXI4
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1
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258
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September 12, 2025
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Ral explicit prediction
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1
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83
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September 9, 2025
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[UVM BackDoor access] Is it possible to have multiple paths to register/memory/register block?
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5
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1426
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September 4, 2025
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P_sequencer and m_sequencer
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12
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55866
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September 1, 2025
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c-uvm synchronization without DPI
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15
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226
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August 26, 2025
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Agent to agent communication
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2
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82
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August 18, 2025
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