I have a test file which is part of a test package, there are some tasks in the tb_top that I want to use. But when I call them from my test file it says “Hierarchical reference from package is not allowed.”
How should this be solved? And why is there a restriction like this ?
Check out this thread
To make the content of a package available in a unit you have to import it. Then it works and you do not need any hierarchical reference.
Hi Chr_sue, I went over your response from other thread as well on the similar topic. I have a test_package. Consider the package as this:
package my_tests
`include my_base_test.sv
`include test_1.sv
`include test_2.sv
`include test_n.sv
endpackage
class test_n extends my_base_test;
task run_phase();
phase.raise_objection(this);
tb_top.task_B();
#10ns;
tb_top.task_A()
endclass
When I call this in run phase of test_n file, I get the error. I basically need to call the tasks defined in tb_top.
Thanks for the response Ahmed, will check this and get back if needed.
I don’t see where your tb_top is and how your test is structured. In teh tb_to you should simply call run_test.
@rabh As already pointed out in the linked thread, anything inside a package cannot directly reference or interact with the design hierarchy. So what are we supposed to do?
We are given one primary mechanism for code in a package (e.g. UVM tests, agents…) to interface with the design: virtual interfaces. You can implement your tasks in the interface or have the testbench react to changing values in the interface. In your example, you can put a task in the interface which in turn calls the task you originally were targeting.
You need a way to get the virtual interface to your UVM environment, and this is done typically through the uvm_config_db, which is essentially a global key-value store singleton. You store the virtual interface in an initial block of your testbench and retrieve it in your UVM environment.
Additionally, UVM provides various HDL access methods like uvm_hdl_force which allow you to interact with the design by specifying hierarchical paths using strings. I would recommend using virtual interfaces when possible and keep these HDL access methods as a backup. Virtual interfaces allow you to trigger on value changes without polling, and I think they promote better organization.
There are always ways to solve such problems. But what @rabh is asking is typical for a Verilog testbench and not for a UVM testbench.
Hi Thomas, Yes I used uvm_hdl_force to get what I eventually wanted to do. Thanks for the reply.
Hi chr_sue, it is a uvm_test bench. I just narrated as to what I wanted to achieve via the code which is above. Might not have been that clear. Thanks for your responses.