Topics tagged Package

Topic	Replies	Views	Activity
Hierarchical reference from package not allowed UVM SystemVerilog , UVM , Package	9	85	May 11, 2025
Importing package SystemVerilog SystemVerilog , Package	2	5144	April 14, 2025
Including same file in 2 different packages SystemVerilog SystemVerilog , Package	1	154	May 29, 2024
Assertion SystemVerilog SystemVerilog , assertion , Package , sequence , systemverilogassertionSVA	2	409	November 17, 2023
Why can my package not keep locally visible? SystemVerilog SystemVerilog , Package	3	329	November 7, 2023
Where is the right place to import a package? content local or not? SystemVerilog SystemVerilog , Package	5	1635	September 25, 2023
How to use packages in class SystemVerilog SystemVerilog , class , Package	3	1007	August 22, 2023
Import package based on define SystemVerilog SystemVerilog , Package , import , define	2	695	March 16, 2023
Why can an interface be recognized in a package, but a class cannot SystemVerilog SystemVerilog , Package	2	1281	December 10, 2022
Module cannot see defines defined in pkg, if this pkg is imported inside module. What is the reason for it? SystemVerilog SystemVerilog , Package , module , package-inside-module	6	921	November 10, 2022
Define from one package are visible in another package SystemVerilog SystemVerilog , Package , macros , system-verilog-package-compilation	7	7625	April 20, 2022
Importing a macro in a class UVM UVM , Package , generate-macro-define	6	1296	October 25, 2021
Compiling a package and an interface into a library SystemVerilog SystemVerilog , Package , interface , compilation , library	1	1122	August 13, 2021
Package Variable imported in multiple modules SystemVerilog SystemVerilog , Package	3	1740	June 14, 2021
How should I do when two package be dependent on each other? UVM UVM , Package	9	2716	April 19, 2021
Can someone tell me how to pass parameters from module to package SystemVerilog SystemVerilog , Package	2	1936	July 30, 2019
Can I declare one time not multiple time for frequently used syntax? UVM UVM , Package	5	1285	July 7, 2019
Compilation error with invalid type and undefined variables SystemVerilog SystemVerilog , Package , enumeration-datatype , Compilation-Error , header-file	6	4590	January 28, 2019
Package undefined UVM UVM , Package	7	3206	October 10, 2018
Overriding classes originating from different packages UVM UVM , Package , factory-overriding-at-run-time , type-parameters	9	2102	August 31, 2018
SystemVerilog include import SystemVerilog SystemVerilog , UVM , Package , import , include	4	2794	April 18, 2018
What to put in a package UVM UVM , Package	4	1951	January 3, 2018
Class inside a package SystemVerilog SystemVerilog , Package	10	6918	September 25, 2017
Location of program file and package SystemVerilog SystemVerilog , Package	1	1032	March 15, 2017
PACKAGE doubt SystemVerilog SystemVerilog , Package	10	3518	November 19, 2015
Compilation error cause by testbench package UVM UVM , Package , include , NPITEM , Compilation-Error	4	5514	September 23, 2015
Duplicate typedef definitions SystemVerilog SystemVerilog , Package , typedef	3	3231	January 15, 2015
Declaring timeunit in package SystemVerilog SystemVerilog , Package , import , timeunit	7	6600	August 11, 2014
Package UVM UVM , Package	1	1836	August 8, 2014
PACKAGE use in SV SystemVerilog SystemVerilog , System-Verilog , Package	1	2049	May 26, 2014