**Error-[UC] Unexpected character
The character ‘2’ is illegal in the context.
“driver.sv”, 73 (expanding macro)
Source info: #(pkg::`CLOCK_WIDTH/2);
**
How to resolve this one NB: Package pkg is imported in top.sv before the compilation of driver.sv
package my_pkg;
`define CLOCK_PERIOD 10
endpackage
module main;
initial begin
$display("clock peripod = %0d",`CLOCK_PERIOD/2);
end
endmodule
It still would have worked without the import. This is because macros get pre-processed and expanded before without any regard to SystemVerilog syntax.