Topics tagged generate-macro-define

Topic	Replies	Views	Activity
Importing a macro in a class UVM UVM , Package , generate-macro-define	6	1109	October 25, 2021
Assertion macros SystemVerilog SystemVerilog , assertion , generate-macro-define , create-macros-or-general-functions , compilation-macro	2	1772	October 19, 2020
Define macro to substitute reg name in regmodel SystemVerilog SystemVerilog , generate-macro-define , Dave-Rich , compilation-macro	1	890	January 27, 2020
Passing hierarchy using `define SystemVerilog SystemVerilog , assertion , generate-macro-define	3	4141	May 16, 2018
String concatenation inside generate block SystemVerilog SystemVerilog , generate-macro-define , define-macro , generate-block , Assignment-inside-generate-block , string-concatenation	4	6234	December 14, 2017
How to change value of the variable which we have given the value using `define? SystemVerilog SystemVerilog , SV , generate-macro-define	4	2197	April 27, 2017
Change instance reference using macro SystemVerilog SystemVerilog , generate-macro-define	3	2161	July 8, 2014