Change instance reference using macro

SystemVerilog
,
1

Hi,

Consider following example. I have such 10 instances in DUT and 50 variables I would like to get in TB. I am trying following generate statement but not working with macro.

module a1();
  reg a;
endmodule : a1

module a2();
  a1 u_a1();
endmodule : a2

module a3();
  a2 u_a2a();
  a2 u_a2b();
  a2 u_a2c();
endmodule : a3;

module dut();
  a3 u_a3();
endmodule : dut

module tb();

// In following, idx needs to be replaced with "a" or "b" or "c"
`define CTRL_REG(idx) dut.u_a3.u_a2``idx``.u_a1

  logic a[3];

  genvar g;
  generate
    for(g=0; g<3; g++) begin
      assign a[g] = `CTRL_REG(string'(g+97)).a; // This is not working, I want to convert 0 to a (as per instance name)
      // How to achieve following using generate statement and macro `define as above
      // assign a[0] = dut.u_a3.u_a2a.u_a1.a;
      // assign a[1] = dut.u_a3.u_a2b.u_a1.a;
      // assign a[2] = dut.u_a3.u_a2c.u_a1.a;
    end
  endgenerate

endmodule : tb

Regards,
Nimesh

2

This cannot be done for 2 reasons. First, macros are preprocessed before any thing else. It will create the following code:

 for(g=0; g<3; g++) begin
   assign a[g] = dut.u_a3.u_a2string'(g+97).u_a1.a;
 end

And u_a2string’(g+97) is not a valid instance path name.

Second, identifiers in SyatemVerilog are symbols, not strings that can be manipulated.

3

In reply to dave_59:

So there is no otherway to reduce or atutomate this code?? At present, I used in-line mux to keep moving…

Kindly suggest, if there is someway to handle this.

Thanks for your response, Dave…!!

Regards,
Nimesh

4

In reply to Nimesh Patel - eInfochips, Inc:

Hi Nimesh,
What you’re trying to do using a string is rather hard due to limitations in the language. However, there is a way to automate your instantiations if you use an array of instances. Here’s what you do:

(1) Change your a3 module to this:

module a3;
   a2 u_a2 [2:0] ();
endmodule

This causes your a2 module to be instantiated 3 times.

(2) Then, using your genvar variable, g, index the instances:

 module tb();
  logic a[3];
 
  genvar g;
  generate
    for(g=0; g<3; g++) begin
      assign a[g] = dut.u_a3.u_a2[g].u_a1.a;
    end
  endgenerate
 
endmodule : tb

That should do it.
Good luck!
-Doug