|
About the SystemVerilog category
|
|
0
|
1201
|
January 1, 2023
|
|
SVA to check a N-stage synchronizer output
|
|
7
|
18
|
December 16, 2025
|
|
Execution of action block in Abort properties (reject_on / accept_on)
|
|
2
|
23
|
December 13, 2025
|
|
Iterator index querying example clarification
|
|
4
|
28
|
December 14, 2025
|
|
Is it possible to use function in assertion but variable widths of the function variables are parameters?
|
|
1
|
21
|
December 12, 2025
|
|
Connection using modports with different signals
|
|
6
|
32
|
December 12, 2025
|
|
AXI, Out of order
|
|
3
|
470
|
December 10, 2025
|
|
Restrictions on fork join_any / join_none
|
|
1
|
47
|
December 10, 2025
|
|
How statements connect to the event scheduler, race condition time
|
|
1
|
28
|
December 9, 2025
|
|
Integer dynamic array sum constraint not working
|
|
5
|
151
|
December 9, 2025
|
|
Difference between always and always_comb
|
|
3
|
690
|
December 8, 2025
|
|
Deep copy using shallow copy
|
|
1
|
27
|
December 6, 2025
|
|
Once a certain sequence occurs that another seq shouldn't occur till simulation ends
|
|
8
|
640
|
December 4, 2025
|
|
SV Constraint Challenge
|
|
13
|
249
|
December 4, 2025
|
|
Time does not strictly flow forward
|
|
2
|
35
|
December 4, 2025
|
|
Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other
|
|
2
|
50
|
November 30, 2025
|
|
Adding and deleting elements of dynamic type at same time
|
|
2
|
46
|
November 29, 2025
|
|
Force a bunch of internal signals when there another particular signal goes high
|
|
2
|
30
|
November 27, 2025
|
|
SVA sequence re-triggers on multiple $fell events – rise_t not updating
|
|
1
|
36
|
November 19, 2025
|
|
Continuous assignment between two inout
|
|
3
|
34
|
November 19, 2025
|
|
Redefine a SV interface port direction in a modport
|
|
2
|
68
|
November 19, 2025
|
|
Resume simulation when any 2 threads out of 3 get completed within fork-join_any
|
|
9
|
4180
|
November 12, 2025
|
|
Verifying synchronours fifo
|
|
3
|
68
|
November 11, 2025
|
|
Question regarding followed by operator in SVA (#-# and #=#
|
|
0
|
49
|
November 11, 2025
|
|
System verilog constraint help
|
|
2
|
88
|
November 11, 2025
|
|
Need help understanding formal verification of asynchronous FIFO
|
|
0
|
59
|
November 3, 2025
|
|
Chained Implications in SVA
|
|
0
|
46
|
November 3, 2025
|
|
Why only ##1 (single delay operator) used in the case of multiple clock sequences?
|
|
2
|
663
|
November 3, 2025
|
|
restricting sequence as long as one variable is asserted
|
|
4
|
67
|
November 2, 2025
|
|
Default value of enumarated varaible is first value of enum
|
|
4
|
56
|
November 1, 2025
|