SystemVerilog

Topic	Replies	Views	Activity
About the SystemVerilog category	0	879	January 1, 2023
Loops inside property block SystemVerilog , assertion , SVA , Assertion-property	0	3	March 24, 2025
Need suggestions for fork join_any argument-pass-by-ref	12	64	March 24, 2025
Incremental compilation or partition compilation	1	16	March 24, 2025
Need to get the repeated value in an array how many times it got repeated and the first index where the repeated value is SystemVerilog	1	6	March 24, 2025
Need to get a constraint with in the 2KB boundary SystemVerilog	0	7	March 24, 2025
Interview Questions on Assertions SystemVerilog , UVM	23	19682	March 22, 2025
How to retrieve the correct values of continuously driven values of DUT in the test bench	0	13	March 22, 2025
Boundaries of $past(d) and current value of d for verifying D flip flop assertion	3	40	March 21, 2025
Why does using a generic interface port (without modports) allow both dut0 and dut1 to drive data and enable without error, while using modports enforces directionality and prevents such assignments? systemverilog-interface	0	12	March 21, 2025
SVA - use different clocks in the property from the sample clock SVA	3	29	March 20, 2025
Need to get the ending address for 180 bytes of data transfer if the starting address is FFF0 and need to consider the AXI 4KB boundary. Bus width is 64 bit	0	19	March 19, 2025
Binding a module to another module's modport interface assertion , SVA , Assertion-Based-Verification , SVA-Assertion , assertion-systemverilog , Assertion-system-verilog	10	74	March 17, 2025
SV bind and Part compilation	3	36	March 18, 2025
Develop 5 threads by using threads concept and make sure if any of 3 threads are completed out of 5 threads then kill other 2 threads SystemVerilog , thread , for-loop-fork-join_none , fork-join_any , fork , disable-fork , fork-join , fork_join , threads , thread-fork	5	43	March 18, 2025
SVA: Package for dynamic and range delays and repeats SystemVerilog , dynamic-delays-dynamic-repeats	13	23674	March 18, 2025
IEEE Std 1800™-2023: 7.12.5 Array mapping method	0	16	March 17, 2025
Write assertion and both cases need to be satisfied in single property Note: when signal B toggles signal A should be stable and should satisfy rise and fall of signal B also	1	43	March 16, 2025
Writing testcases for different frequency	4	55	March 16, 2025
We have 32 bit address in which 1 bit is one . write a condition to get it in descending order?	1	43	March 15, 2025
32-bit variable is present. it will has some random value. we need to return the index value whichever has the 1 for the first time. ex:68 number is there, if you write in binary format that is 01101000. in this it hits 1 for the first time	2	32	March 13, 2025
Constraint to make sure each value gets randomized at least once	4	45	March 13, 2025
How to Pass a Virtual Interface to a generic class	2	40	March 13, 2025
Question on clocking blocks and races	0	36	March 12, 2025
Where is pre_randomize() used? SystemVerilog	5	1584	March 12, 2025
How to achieve fork-join_none and fork join_any functionality using fork-join SystemVerilog , System-Verilog , fork-join_any , fork-join_none , fork-join , threads	6	1047	March 12, 2025
Use fork join_none inside loop with behaviour of fork join SystemVerilog , thread , threads , thread-fork	5	41	March 11, 2025
SV Constraint Challenge systemverilog-constraint	12	72	March 11, 2025
Randomly Divide Fixed Memory into Non-Overlapping Blocks	0	33	March 10, 2025
Are package functions synthesizable? Do I need to declare them automatic? SystemVerilog , packages	1	30	March 10, 2025