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About the SystemVerilog category
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0
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1209
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January 1, 2023
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Time does not strictly flow forward
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3
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58
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December 20, 2025
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Displaying associative array elements in Specific order
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2
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30
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December 18, 2025
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SVA to check a N-stage synchronizer output
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9
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49
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December 18, 2025
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Execution of action block in Abort properties (reject_on / accept_on)
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2
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27
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December 13, 2025
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Iterator index querying example clarification
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4
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38
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December 14, 2025
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Is it possible to use function in assertion but variable widths of the function variables are parameters?
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1
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35
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December 12, 2025
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Connection using modports with different signals
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6
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40
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December 12, 2025
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AXI, Out of order
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3
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487
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December 10, 2025
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Restrictions on fork join_any / join_none
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1
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67
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December 10, 2025
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How statements connect to the event scheduler, race condition time
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1
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32
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December 9, 2025
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Integer dynamic array sum constraint not working
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5
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156
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December 9, 2025
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Difference between always and always_comb
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3
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698
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December 8, 2025
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Deep copy using shallow copy
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1
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42
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December 6, 2025
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Once a certain sequence occurs that another seq shouldn't occur till simulation ends
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8
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644
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December 4, 2025
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SV Constraint Challenge
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13
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259
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December 4, 2025
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Query on generating rand 2D array with sum of set bits equal to specific value and bits must be connected to each other
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2
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60
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November 30, 2025
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Adding and deleting elements of dynamic type at same time
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2
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53
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November 29, 2025
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Force a bunch of internal signals when there another particular signal goes high
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2
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36
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November 27, 2025
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SVA sequence re-triggers on multiple $fell events – rise_t not updating
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1
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39
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November 19, 2025
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Continuous assignment between two inout
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3
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37
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November 19, 2025
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Redefine a SV interface port direction in a modport
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2
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68
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November 19, 2025
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Resume simulation when any 2 threads out of 3 get completed within fork-join_any
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9
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4194
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November 12, 2025
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Verifying synchronours fifo
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3
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70
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November 11, 2025
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Question regarding followed by operator in SVA (#-# and #=#
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0
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49
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November 11, 2025
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System verilog constraint help
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2
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94
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November 11, 2025
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Need help understanding formal verification of asynchronous FIFO
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0
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59
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November 3, 2025
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Chained Implications in SVA
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0
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50
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November 3, 2025
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Why only ##1 (single delay operator) used in the case of multiple clock sequences?
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2
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667
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November 3, 2025
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restricting sequence as long as one variable is asserted
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4
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70
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November 2, 2025
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