|
How can i know the differnce between static and dynamic class handle? an example code please
|
|
1
|
29
|
August 12, 2025
|
|
System Verilog fork join_none with for loop & delay
|
|
5
|
592
|
August 12, 2025
|
|
Using assertion to detect glitch?
|
|
7
|
14343
|
August 11, 2025
|
|
Procedural concurrent assertions within for loop
|
|
5
|
181
|
August 10, 2025
|
|
Write a constraint to divide values of one queue into three queues so that all 3 queues have unique values
|
|
6
|
515
|
August 8, 2025
|
|
Tackling a constraint in post_randomize()
|
|
5
|
385
|
August 8, 2025
|
|
System verilog, Constraint
|
|
6
|
512
|
August 8, 2025
|
|
Randomize an array using constraints such that no number in the array repeats more than twice
|
|
11
|
2189
|
August 6, 2025
|
|
Constraining WStrb
|
|
3
|
217
|
August 6, 2025
|
|
Using ternary operator as an alternative to if-else in consequent
|
|
3
|
68
|
August 5, 2025
|
|
Randomization and control
|
|
4
|
76
|
August 3, 2025
|
|
Packed dynamic array of type "BIT"
|
|
1
|
46
|
July 30, 2025
|
|
Queue and mailbox
|
|
14
|
47409
|
July 30, 2025
|
|
Poll for a status register until we see desired read value
|
|
2
|
55
|
July 29, 2025
|
|
Accessing invalid address is not working
|
|
6
|
43
|
July 28, 2025
|
|
Constrained Memory Block Allocation
|
|
4
|
70
|
July 28, 2025
|
|
SVA: Implementing Dynamic Delay using procedural Immediate assertion
|
|
5
|
124
|
July 27, 2025
|
|
Timeout task different behavior under different optimization
|
|
3
|
55
|
July 27, 2025
|
|
Clock oscillator for testbench
|
|
3
|
60
|
July 27, 2025
|
|
Purpose of wait fork
|
|
1
|
70
|
July 24, 2025
|
|
Interface and dut signals are not matching in case of APB PSELx signals
|
|
2
|
32
|
July 24, 2025
|
|
Potential hang with nested fork
|
|
1
|
62
|
July 23, 2025
|
|
Immediate assertion not taking either of its action blocks
|
|
3
|
39
|
July 22, 2025
|
|
Assertion race condition
|
|
1
|
56
|
July 22, 2025
|
|
I want to write a constraint such that in 26 bit address I get the consecutive 4bits with patter 1011 70% of the time and 30 % of the time we don't care
|
|
9
|
111
|
July 22, 2025
|
|
Casting between signed and unsigned values and variables
|
|
2
|
75
|
July 19, 2025
|
|
System verilog constraint
|
|
3
|
113
|
July 19, 2025
|
|
Wait for variable cycles number before triggering property
|
|
3
|
73
|
July 18, 2025
|
|
Possible alternative to multiple $test$plusargs
|
|
2
|
57
|
July 15, 2025
|
|
Coverage bins sampling an uninitialized virtual interface object
|
|
7
|
78
|
July 15, 2025
|