Assertion that checks if two clocks are synchronized forever based on a request pulse?

SystemVerilog
1

I want to write an assertion that waits for a pulse to check if two clocks are synchronized for the rest of the simulation. I know the following is incorrect but it is pseudo code for what I want to perform. I am having trouble getting it to sync and for it be continous.

property clk_equals_clk2;
@(posedge clk_check_req)
disable iff (!rst)
enable |-> $rose(clk2) && $rose(clk); // I’m not sure how to get it to run continuously
endproperty

2

See next post with the corrections.

3

Took the always off, and the reset

// Code your testbench here
// or browse Examples
module top; 
    bit clk0, clk1,rst=0,enable,  clk_check_req;
    realtime period =3ns; 
    int p1, f1, n=0;     
    initial forever #(period/2) clk0= #n !clk0;  
    initial forever #(period/2) clk1=!clk1;  

    property clk0_equals_clk1;
        realtime v;
        @(posedge clk_check_req)
      
      //  disable iff (!rst)
      
     // enable |->
      (@(posedge clk0) (1, v=$realtime) ##0 @(posedge clk1) $realtime-v ==0) ; 
    endproperty
    ap_clk0_equals_clk1: assert property(clk0_equals_clk1) p1++; else f1++;

    initial begin       
        $dumpfile("dump.vcd"); $dumpvars;  
      @(posedge clk0) enable <=1;
      @(posedge clk0) enable <= 1;
        repeat(10)  @(posedge clk0);   
        n=1;
        repeat(10)  @(posedge clk0);  
        $stop; 
    end 
endmodule