Is there really a need to use constraints for something that can easily be done with a function call? Also, if you can write constraints, what should the randomize function do when all bits are ones?
Ben
In reply to ben@SystemVerilog.us:
A const cast means treat the expression as a constant value (I.e. non-random) value. The expression gets evaluated before randomization and is treated like a state variable.
i am getting this error plz help me OUT
// code here
class packet;
rand bit[10:0] varb = 11’b10000000000;
constraint pattern { varb == const’( {1’b1, varb[10:1]} ); }
endclass
module constr_blocks;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
pkt.randomize();
$display(“\t value = %0d”,pkt.varb);
end
end
endmodule
if I have some thing like this rand bit [4:0] variable[]; size of variable is 5, and i want to generate pattern like variable[0] = 10000; variable[1] = 11000, variable[2] = 11100, variable [3] = 11110, variable[4] = 11111; Why does the following constraint misbehave/not working?
class problem9;
rand bit [4:0] variable[];
bit [4:0] variable_1[5];
constraint on_variable {
foreach(variable[i]) {
if(i !=0) {
variable[i] == (variable[i-1]) | (1<<(4-i));
}
else {
variable[0] == 1 << 4 ;
}
}
}
constraint size{
variable.size()==5;
}
endclass
module check;
problem9 p9;
initial
begin
p9 = new();
p9.randomize();
foreach(p9.variable[i]) begin
$display("i = %0d, variable = %0b",i, p9.variable[i]);
end
foreach(p9.variable_1[i]) begin
if(i != 0) begin
p9.variable_1[i] = p9.variable_1[i-1] | 1 << (4-i);
end
else
p9.variable_1[0] = 1 << 4;
$display("p9.variable_1 here = %0b", p9.variable_1[i]);
end
end
endmodule
I am getting the output for variable_1 where constraint/randomization is not involved. but for variable I get an output as:
i = 0, variable = 10000
i = 1, variable = 10110
i = 2, variable = 10000
i = 3, variable = 10010
i = 4, variable = 11000