Pattern Generation

I have a 50 bit variable, I want to generate a pattern as shown in example under. How do I write a constraint for it.

For Example
rand bit[10:0] var; (Taking an example of 10 bit variable actual pattern needed is for a 50 bit variable)

Pattern
1000000000
1100000000
1110000000
1111000000
1111100000
1111110000
1111111000
1111111100
1111111110
1111111111

Is there really a need to use constraints for something that can easily be done with a function call? Also, if you can write constraints, what should the randomize function do when all bits are ones?
Ben

In reply to nishitk:

rand bit[10:0] varb = 11'b10000000000;
constraint pattern { varb == const'( {1'b1, varb[10:1]} ); }

In reply to dave_59:

Why the need for the const?

In reply to ben@SystemVerilog.us:
A const cast means treat the expression as a constant value (I.e. non-random) value. The expression gets evaluated before randomization and is treated like a state variable.

In reply to dave_59:

It helps. Thanks Dave !

In reply to dave_59:

In reply to nishitk:

rand bit[10:0] varb = 11'b10000000000;
constraint pattern { varb == const'( {1'b1, varb[10:1]} ); }

i am getting this error plz help me OUT
// code here
class packet;
rand bit[10:0] varb = 11’b10000000000;
constraint pattern { varb == const’( {1’b1, varb[10:1]} ); }
endclass

module constr_blocks;
initial begin
packet pkt;
pkt = new();
repeat(10) begin
pkt.randomize();
$display(“\t value = %0d”,pkt.varb);
end
end
endmodule

output:ERROR VCP7501 “Undeclared type: const.” “testbench.sv” 5 59

In reply to Rohi_417:

It looks like your tool has not implemented a const cast. Maybe you have an older version. Please contact your vendor for support.

if I have some thing like this rand bit [4:0] variable[]; size of variable is 5, and i want to generate pattern like variable[0] = 10000; variable[1] = 11000, variable[2] = 11100, variable [3] = 11110, variable[4] = 11111; Why does the following constraint misbehave/not working?

class problem9;
	
	rand bit [4:0] variable[];
	
	bit [4:0] variable_1[5];

	constraint on_variable {
		foreach(variable[i]) {
			if(i !=0) { 
			variable[i] == (variable[i-1]) | (1<<(4-i));
			}
			else {
			variable[0] == 1 << 4 ;
			}
			}
		
		}
	constraint size{
		variable.size()==5;
	} 
endclass

module check;
	problem9 p9;

	initial
		begin
			p9 = new();
			p9.randomize();
			foreach(p9.variable[i]) begin
			$display("i = %0d, variable = %0b",i, p9.variable[i]);
			end
			foreach(p9.variable_1[i]) begin
				if(i != 0) begin
				p9.variable_1[i] = p9.variable_1[i-1] | 1 << (4-i);
				end
				else 
				p9.variable_1[0] = 1 << 4;
				$display("p9.variable_1 here = %0b", p9.variable_1[i]);
			end
		end
endmodule

I am getting the output for variable_1 where constraint/randomization is not involved. but for variable I get an output as:
i = 0, variable = 10000
i = 1, variable = 10110
i = 2, variable = 10000
i = 3, variable = 10010
i = 4, variable = 11000

You have a problem with operator precedence in your constraint. Check the precedence of bitwise ‘or’ (|).

Here’s one way to do this.

package learning; 
     import uvm_pkg::*;  
     `include "uvm_macros.svh"

     class packet extends uvm_object;
         `uvm_object_utils(packet)

         function new(string name = "packet");
             super.new(name);
         endfunction

         static int count = 1; 
         rand bit [10:0] pattern;
         bit [10:0] p = ~0;

         constraint default_c {
             pattern == (p << ($bits(pattern) - count));
         }

         function void post_randomize();
             if ($bits(pattern) == count) count = 1; else count++;
         endfunction

         virtual function void printInfo();
             `uvm_info(get_type_name, $sformatf("pattern = %b", pattern), UVM_LOW)
         endfunction

     endclass


     class test extends uvm_test;
         `uvm_component_utils(test)

         rand packet pkt;

         function new(string name="test", uvm_component parent);
              super.new(name, parent);
         endfunction

         task run_phase(uvm_phase phase);
             super.run_phase(phase); 
             repeat (50) begin
                 pkt = packet::type_id::create("pkt");
                 assert(pkt.randomize());
                 pkt.printInfo();
             end
         endtask

     endclass


endpackage


module top();
    `include "uvm_macros.svh"
    import uvm_pkg::*;
    import learning::*;

    initial begin
        run_test("test");
    end
endmodule

ya got it, thanks Dave.

class abc;
  rand bit[9:0] a,b;
  static bit[9:0] count;
  constraint a_c{
    a == 10'b1111_1111_11<< count;
  }
  
  function void post_randomize();
    count++;
    foreach(a[i]) begin 
      b[i] = a[9-i];
    end
    b = ~b;
    $display("count =%0p a =%b", count, b);
  endfunction
  
endclass
  
  module tb;
   abc abc_inst;
  initial begin 
    abc_inst = new();
    repeat(10)
    abc_inst.randomize();

  end
endmodule