In reply to ben@SystemVerilog.us:
A const cast means treat the expression as a constant value (I.e. non-random) value. The expression gets evaluated before randomization and is treated like a state variable.
In reply to ben@SystemVerilog.us:
A const cast means treat the expression as a constant value (I.e. non-random) value. The expression gets evaluated before randomization and is treated like a state variable.