Syntax error: token is '('

SystemVerilog
1

Hi,

The following code of a file gives syntax error.

module dut_top;
 univ_intf u1;
 u1.print_hello();
endmodule
interface univ_intf();
task print_hello();
    $display("Hi");
endtask
endinterface

As I understand interface can have tasks defined within them & these tasks can be calle from outside module. I am not sure why it’s complaining about the Syntax error in :
u1.print_hello();
Token is ‘(’.

Can anyone please help me on this. Thanks.

2

The problem is with the syntax inside your module. A call to a task must be inside procedural code. You need to write

initial  u1.print_hello();

Another problem is you are missing ()'s after the interface instance name.

 univ_intf u1();