In this distribution constraint, I am not getting 50% of time exactly 5 bits are set and remaining 50% of time number of bits set are not 5

/*
Write a constraint in systemverilog
----------------------------
1. In a given array N, 5 bits are set 50% of the time
2. 5 bits are not set remaining 50% of the time
*/
class AC;
rand bit[9:0] N;
constraint c1 { N dist { $countones(N)==5 := 50, $countones(N)!=5 := 50 }; }
endclass
module TB;
AC ac;
initial
begin
repeat(10)
begin
ac = new();
ac.randomize();
$display("N is %b", ac.N);
end
end
endmodule

N is 0000000000
N is 0000000000
N is 0000000001
N is 0000000000
N is 0000000001
N is 0000000001
N is 0000000000
N is 0000000001
N is 0000000000
N is 0000000001

@aaronferrucci, The verbose problem statement is "50% of the time randomize() gets called, 5 bits must be randomly set to 1 out of the 10 bits in variable N. The other 50% of the time, some number of bits other that 5 bits must be set.

hi @dave_59 ,
can you explain why the above code tried by @dvuvmsv doesn’t work?

//Q. Write a constraint for a 10 bit variable so that; → 10% of the time 1 bit in en is high → 10% of the time 2 bits in en are high … → 10% of the time all 10 bits in en are high.

class example;
rand bit [9:0] arr;
constraint arr_dist{
arr dist{($countones(arr)==1) := 10, ($countones(arr)==2) := 10,$countones(arr)==3 := 10, $countones(arr)==4 := 10, $countones(arr)==5 := 10, $countones(arr)==6 := 10, $countones(arr)==7 := 10, $countones(arr)==8 := 10, $countones(arr)==9 := 10, $countones(arr)==10 := 10};
}
function void print();
$display("value of array is %b",arr);
// $display("value of max_sum is %d",max_sum);
endfunction
endclass

I want to try generating the arr variable in above fashion, i’m also getting all 0 as output after randomization.

Think of a dist constraint as a set membership inside expression first. It is basically (arr inside {0,1}) because the result of the two == equality expressions can only be true ‘1’ or false ‘0’.