Verilog blocking and non-blocking

SystemVerilog
1 
module test(a,b,c,z);
input a,b,c;
output z;
reg z;
always@(*)
begin
z<=a;
z<=z&b;
z<=z^c;
end
endmodule

//Please explain the inferred hardware.

2

If there are multiple NBAs scheduled to the same variable in the same process, last assignment wins. This is effectively the same as

always@(*) z<=z^c;

Which would be an infinite oscillating feedback loop if c is 1.

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