Which method is best to choose

SystemVerilog
1

Hi There,

In specification I have a signal called HBURST(is kind of opcode it can be increment 4, 8) that means if hburst is incr 4 then address must be in increment fashion based on hsize
for example
hburst = incr 4 and hsize is 2 bytes then the address fashion is 2, 4, 6, 8
hburst = incr 4 and hsize is4 bytes then the address fashion is 0, 4, 8, 12

for this feature I have two ideas to generate this fashion

  1. to write a constraint in the transaction class
rand int haddr[];
rand int hburst; // hburst must be incr 4 or 8
rand int hsize; // hsize must be 0: 1, 1:2, 2:4, bytes

constraint f {
if(hburst == incr4)
haddr.size() == 4;
else
haddr.size() == 8;
foreach(haddr[i])
{
if(i!=0)
haddr[i] == haddr[i-1] + 2**hsize;
}
}
  1. one is implement the address based on transaction packet
//lets say transaction packet gives only hburst and hsize and start of haddr and the remaining body will be implemented in driver class
// the remaining part of the haddr will be generated in driver class and send to dut

I got two ideas to implement this feature in my school project, can anyone explain me which method is best and why?

Thanks

2

In general the best thing to do is generating everything in a single call to randomize() for each transaction. This makes adding new constraints easier, more maintainable, and overridable. Do it this way unless you have a good reason not to.

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