Topic	Replies	Views	Activity
Access VHDL hierarchical objects from a SV testbench SystemVerilog VHDL	1	107	June 26, 2024
Verification of a vhdl AXI4 model master using systemverilog.(ERROR) SystemVerilog VHDL	0	134	April 2, 2024
What is std_logic_vector16(15 downto 0)? UVM SystemVerilog , UVM , VHDL	2	753	November 16, 2021
How to implement UVM testbench for DUT VHDL? UVM UVM , VHDL , UVM-modelsim	3	1282	November 28, 2020
Bind statements to VHDL generate block SystemVerilog SystemVerilog , bind , generate , VHDL	1	1018	August 12, 2019
Unconstrained Arrays equivalent in SystemVerilog SystemVerilog SystemVerilog , VHDL , systemverilog-Arrays	2	2514	March 1, 2019
How to override VHDL generics using vopt -G option SystemVerilog SystemVerilog , override , VHDL , vopt , generic	5	8817	April 20, 2018
Illegal sequential statement SystemVerilog SystemVerilog , VHDL	2	5237	January 16, 2018
Approach to disconnect RTL driver and bind AHB interface instead UVM UVM , bind , VHDL	2	1638	November 19, 2015
Usage of bind statement with VHDL DUT UVM UVM , bind , SV , VHDL	5	8918	November 18, 2015
Can modports be used to isolate logic signals in an interface from tasks? SystemVerilog SystemVerilog , modport , interface , VHDL , tasks	2	2581	June 11, 2015
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	13434	September 23, 2014
Probing VHDL signal in Verilog Module SystemVerilog SystemVerilog , VHDL	1	1756	June 28, 2014

VHDL