Access VHDL hierarchical objects from a SV testbench

SystemVerilog
1

Hello,
Is there a standard(non simulator vendor dependent) way to access internal design names from a SV testbench(the design is writeten in VHDL)
In my simulator I write:

assign my_SV_signal = design_path.VHDL_signal_name

but it seems that it does not work on other simulators, so I need to use other methods like using simulator specific system functions
Thanks

2

Unfortunately, there is no standard for interoperability between standards (at least in the EDA world).

You migt be able to wrap the VHDL reference in a macro, and have the macro defined vendor specific.