Topics tagged Verilog

Topic	Replies	Views	Activity
Valid Data Filter SystemVerilog SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint	2	86	February 16, 2025
Synthesizability of the following code SystemVerilog Verilog , InterviewQuestions , synthesis , synthesizable	0	22	February 12, 2025
Need to printing the values in binary with leading zeros SystemVerilog SystemVerilog , UVM , testbench , Verilog	1	251	May 23, 2024
Case statement range SystemVerilog Verilog	3	191	May 17, 2024
Part vector selection SystemVerilog Verilog	3	210	May 17, 2024
What happens when we assign a value to a net at the time of declaration? SystemVerilog Verilog	4	245	May 10, 2024
How to pass an array in verilog funcion SystemVerilog SystemVerilog , Verilog , FunctionArgument	10	777	December 6, 2023
Explanation of %p in verilog $display function SystemVerilog SystemVerilog , display , Verilog	1	1414	October 19, 2023
Is there a way to make the force value propagate beyond the double assigned wire SystemVerilog SystemVerilog , Verilog , signal_force , FORCE , CPU	1	259	September 12, 2023
System verilog compiler directive Q SystemVerilog SystemVerilog , System-Verilog , Verilog , RAL-UVM , compiler	0	446	May 13, 2023
Long delay not working properly in Verilog SystemVerilog SystemVerilog , Verilog , Altera , quartus , cyclone-II	4	794	April 27, 2023
Swap bit SystemVerilog SystemVerilog , Verilog	2	800	March 29, 2023
Signal delay by X clock cycles in System Verilog SystemVerilog SystemVerilog , Verilog , Delay , clock , signal	5	24229	December 9, 2022
Need help with the error SystemVerilog SystemVerilog , error , Verilog , python , base_test-uvm_tlm_fifo , help	1	732	November 14, 2022
Control over randomization without using constraint SystemVerilog SystemVerilog , constraint-randomization , Verilog	3	798	July 22, 2022
Gate level modeling for pull up termination SystemVerilog SystemVerilog , Verilog , gatelevelmodelling , gate-level-modeling	1	1077	December 25, 2021
Shifting operation SystemVerilog SystemVerilog , Verilog	3	941	July 26, 2021
T flipflop clock cannot be seen in simulation graph SystemVerilog SystemVerilog , Verilog , t-flipflop	4	672	July 1, 2021
@always position SystemVerilog SystemVerilog , Verilog , always	2	702	January 16, 2021
Non- Blocking assignments with Transport delay SystemVerilog SystemVerilog , Verilog	1	1304	November 1, 2020
Functions with assign statements SystemVerilog SystemVerilog , Verilog , function-call	3	2811	November 1, 2020
Can you use a radix to print readable names in Verilog (or SystemVerilog)? SystemVerilog SystemVerilog , Verilog , radix	2	1039	November 1, 2020
How to use assign inside $test$plusargs in systemverilog? SystemVerilog SystemVerilog , UVM , Verilog	4	5137	July 12, 2020
Recent Verilog HDL Basics Tutorial SystemVerilog SystemVerilog , Verilog	2	990	June 10, 2020
Do we have any other method to achieve FORCE and RELEASE SystemVerilog SystemVerilog , SV , Verilog , uvm-dynamicarray , FORCE , RELEASE	1	733	April 13, 2020
Is it illegal/not recommended that the RHS of an inferred FF should not change in Active region along with Clock of the FF? SystemVerilog SystemVerilog , Verilog , Active-Region	1	675	March 9, 2020
Find the error in the shift operator usage. output not generated properly SystemVerilog SystemVerilog , Verilog , logical-shift-operator , shift-operator-usage	1	724	June 17, 2019
How does verilog deal with the fact that it doesn't allow user defined types SystemVerilog SystemVerilog , Verilog , 2d-array-verilog	5	1067	March 27, 2019
How does Synthesis of D Flip FLop differs if it is coded using Blocking assignment and Non Blocking assignment SystemVerilog SystemVerilog , Verilog	5	4561	January 28, 2019
Connecting port to higher width wire in verily SystemVerilog SystemVerilog , Verilog	1	2104	January 12, 2019