Need to printing the values in binary with leading zeros

SystemVerilog
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1

I was trying to create a file which tracks signals during simulation and print in a log file. So i am trying to capture REQ/ACK signals during simulation below is sample code

 always @(*) begin
      if (req !== prev_req || ack !== prev_ack) begin
            fh = $fopen(file_name, "a");
            $fwrite(fh, "@ %t   |  %0b        |   %0b  \n", $realtime, req, ack);
            prev_req = req;
            prev_ack = ack;
            $fclose(fh);
      end
  end

So i am able to get prints in below is sample it was captured

@ 93 ns | 1 | 0
@ 95 ns | 1 | 1
@ 97 ns | 11 | 1
@ 98 ns | 1000111 | 111
@ 99 ns | 1000111 | 1000111

but i need all bits status every time , like below

@ 93ns | 000000001 | 000000000
@ 95ns | 000000001 | 000000001
@ 97 ns | 000000011 | 000000001
@ 98 ns | 001000111 | 000000111
@ 99 ns | 001000111 | 001000111

Is they is anyway i can do it ?

2

Use %b instead of %0b. The 0 is asking to suppress leading 0’s