Topics tagged testbench

Topic	Replies	Views	Activity
Pattern Detector 10110 in SV (no FSM) SystemVerilog SystemVerilog , testbench , System-Verilog , SV , queue , systemverilog-Arrays , queues-systemverilog	1	356	February 19, 2025
How to end background reg access sequences gracefully UVM SystemVerilog , testbench , uvm_sequence	1	134	September 11, 2024
Need to printing the values in binary with leading zeros SystemVerilog SystemVerilog , UVM , testbench , Verilog	1	335	May 23, 2024
There are 2 agents. can Monitor from agent A communicate with Sequencer of Agent B. If yes how? UVM UVM , testbench	3	492	February 28, 2024
Asynchronous Stable Signal SVA SystemVerilog SystemVerilog , assertion , testbench , SVA , property	14	1149	August 17, 2023
ASYNCHRONOUS FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design? SystemVerilog SystemVerilog , testbench , System-Verilog , fifo , asynchronous	1	741	January 13, 2023
Multiple scoreboards in UVM TB framework UVM UVM , testbench , UVM-scoreboard	3	1234	September 12, 2022
Pulse generator Task SystemVerilog SystemVerilog , testbench , pulsecounter	1	951	March 30, 2022
How to change parameter of systemverilog testbench with Makefille SystemVerilog SystemVerilog , testbench , parameter , makefile	1	1133	November 18, 2021
Find test bench issue UVM UVM , testbench	1	451	November 12, 2021
[SystemVerilog] Guideline on when to use logical (`==`) vs. case equality (`===`) SystemVerilog SystemVerilog , testbench	2	1477	September 29, 2021
Trying to test a simple test bench but getting errors from Quartus prime SystemVerilog SystemVerilog , testbench , error	1	873	April 12, 2021
Creating a basic coverage model for FFT Coverage SystemVerilog , Coverage , testbench	3	1342	October 5, 2020
Assigning Packed Type to Unpacked Type SystemVerilog SystemVerilog , testbench , packed , unpacked	3	3446	September 30, 2020
Data checker SystemVerilog SystemVerilog , testbench , SIPO , data-checker	1	1091	March 17, 2019
Race condition setting config from testbench parameter UVM UVM , testbench , uvm_config_db , DUT-parameters	3	2283	August 1, 2016
Running tcl commands from within my systemverilog testbench SystemVerilog SystemVerilog , testbench , transcript , tcl	2	8166	March 4, 2015
Multi-threaded UVM Testbench UVM UVM , testbench , multi-threading	2	2346	May 4, 2014
In UVM TB,do we need config_obj both at env and agent level,only at agent level will not suffice? UVM UVM , testbench , config_obj	4	2990	December 18, 2013

Pattern Detector 10110 in SV (no FSM)

SystemVerilog

SystemVerilog , testbench , System-Verilog , SV , queue , systemverilog-Arrays , queues-systemverilog

1

356

February 19, 2025

How to end background reg access sequences gracefully

UVM

SystemVerilog , testbench , uvm_sequence

1

134

September 11, 2024

Need to printing the values in binary with leading zeros

SystemVerilog

SystemVerilog , UVM , testbench , Verilog

1

335

May 23, 2024

There are 2 agents. can Monitor from agent A communicate with Sequencer of Agent B. If yes how?

UVM

UVM , testbench

3

492

February 28, 2024

Asynchronous Stable Signal SVA

SystemVerilog

SystemVerilog , assertion , testbench , SVA , property

14

1149

August 17, 2023

ASYNCHRONOUS FIFO: Should I focus only on the top_level or maybe focus on the modules within the top_level design?

SystemVerilog

SystemVerilog , testbench , System-Verilog , fifo , asynchronous

1

741

January 13, 2023

Multiple scoreboards in UVM TB framework

UVM

UVM , testbench , UVM-scoreboard

3

1234

September 12, 2022

Pulse generator Task

SystemVerilog

SystemVerilog , testbench , pulsecounter

1

951

March 30, 2022

How to change parameter of systemverilog testbench with Makefille

SystemVerilog

SystemVerilog , testbench , parameter , makefile

1

1133

November 18, 2021

Find test bench issue

UVM

UVM , testbench

1

451

November 12, 2021

[SystemVerilog] Guideline on when to use logical (`==`) vs. case equality (`===`)

SystemVerilog

SystemVerilog , testbench

2

1477

September 29, 2021

Trying to test a simple test bench but getting errors from Quartus prime

SystemVerilog

SystemVerilog , testbench , error

1

873

April 12, 2021

Creating a basic coverage model for FFT

Coverage

SystemVerilog , Coverage , testbench

3

1342

October 5, 2020

Assigning Packed Type to Unpacked Type

SystemVerilog

SystemVerilog , testbench , packed , unpacked

3

3446

September 30, 2020

Data checker

SystemVerilog

SystemVerilog , testbench , SIPO , data-checker

1

1091

March 17, 2019

Race condition setting config from testbench parameter

UVM

UVM , testbench , uvm_config_db , DUT-parameters

3

2283

August 1, 2016

Running tcl commands from within my systemverilog testbench

SystemVerilog

SystemVerilog , testbench , transcript , tcl

2

8166

March 4, 2015

Multi-threaded UVM Testbench

UVM

UVM , testbench , multi-threading

2

2346

May 4, 2014

In UVM TB,do we need config_obj both at env and agent level,only at agent level will not suffice?

UVM

UVM , testbench , config_obj

4

2990

December 18, 2013