What operators constitute a multi-threaded sequence
|
|
1
|
40
|
October 16, 2025
|
AHB Write data (HWDATA) Stability Check during AHB write waited states. (SVA)
|
|
0
|
28
|
September 19, 2025
|
Detect AHB data-phase of AHB Write/Read Access and check the write/read data is valid. (SVA)
|
|
0
|
30
|
September 19, 2025
|
Assertion to check the following waveform
|
|
5
|
108
|
September 9, 2025
|
Understanding the working of Embedded Concurrent Assertions
|
|
8
|
136
|
September 8, 2025
|
Doubts on disable iff clause in SVA
|
|
2
|
59
|
August 31, 2025
|
SVA Assertions using only $realtime and nested implications
|
|
5
|
246
|
August 13, 2025
|
Procedural concurrent assertions within for loop
|
|
5
|
204
|
August 10, 2025
|
Using ternary operator as an alternative to if-else in consequent
|
|
3
|
81
|
August 5, 2025
|
SVA: Implementing Dynamic Delay using procedural Immediate assertion
|
|
5
|
145
|
July 27, 2025
|
Working of sequence method 'matched'
|
|
1
|
105
|
June 21, 2025
|
Regarding disable iff
|
|
3
|
102
|
June 20, 2025
|
Query regarding witness for vacuosly passing assertions in Formal Verification
|
|
1
|
49
|
June 12, 2025
|
To check that a signal toggles at least once every 20 cycles
|
|
8
|
203
|
June 9, 2025
|
Liveness and safety property in formal verification
|
|
1
|
62
|
May 29, 2025
|
Access internal reg and local param of the RTL from the sva file
|
|
2
|
59
|
May 21, 2025
|
FIFO module assertion
|
|
2
|
366
|
May 19, 2025
|
Assertion to check reset is synchronised to the input clock
|
|
2
|
77
|
May 14, 2025
|
Questions on disable iff
|
|
1
|
102
|
May 1, 2025
|
Working of strong operator & final block
|
|
0
|
51
|
April 29, 2025
|
Working of disable iff
|
|
4
|
171
|
January 4, 2025
|
Formal Assumption to Model a FIFO Push (with a delay)
|
|
3
|
90
|
April 29, 2025
|
Usage of Throughout and Intersect in SVA
|
|
5
|
4202
|
April 29, 2025
|
SVA and clock domain crossing
|
|
9
|
5906
|
April 18, 2025
|
Assertion on gated clock and after some time ungated clock
|
|
3
|
126
|
April 10, 2025
|
Binding a module to another module's modport interface
|
|
13
|
196
|
April 2, 2025
|
Loops inside property block
|
|
1
|
101
|
March 24, 2025
|
SVA - use different clocks in the property from the sample clock
|
|
3
|
67
|
March 20, 2025
|
Overlap between the two asynchronous reset signals
|
|
4
|
127
|
March 3, 2025
|
Register value is updated based on handshake on B Channel
|
|
0
|
46
|
February 27, 2025
|