Loops inside property block

SystemVerilog
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1

i’m wondering may i can use loops inside a property block of assertion. below i have given a example. here i’m wondering instead of giving the same code with increasing index, may i can use foreach loop. does property support it?. what if i use a function inside the property and inside the function i have declared the foreach loop. does it work?

property pslverr_invalid_addr; 
  @(posedge PCLK) 
  disable iff (!PRESETn)
  ((PSEL[0] && PENABLE && PREADY && !(PADDR inside {[SLAVE_ADDR[0].start_addr:SLAVE_ADDR[0].end_addr]})) ||
   (PSEL[1] && PENABLE && PREADY && !(PADDR inside {[SLAVE_ADDR[1].start_addr:SLAVE_ADDR[1].end_addr]})) ||
   ((PSEL[2] && PENABLE && PREADY && !(PADDR inside {[SLAVE_ADDR[2].start_addr:SLAVE_ADDR[2].end_addr]}))) 
  |-> $rose(PSLVERR);  //
endproperty
2

You can use a function as part of a Boolean expression, although there are a few restrictions. All the sample values need to be passed in as arguments to the function. The function cannot have any side-effect. See 16.6 Boolean expressions in the IEEE 1800-2023 SystemVerilog LRM