Assertion on gated clock and after some time ungated clock

SystemVerilog
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1

Following is my question, i have tried to represent in wave form fashion .

image
image1735×414 13.3 KB

Question in writing:
1)@(posedge clk_delayed) disable iff reset=0 | check_enable=0
2) When ever FHCEn =1 is asserted in some cycles as shown i diagram check for sigs[58:0] = 0 while FHCEn remain 1 sigs should be 0 once FHCEn becomes zero stop checking

Following is my code attempted

   property sigs_low_when_har_set_prop;
     @(posedge clk_delayed) disable iff ((reset == 1'b0) || (check_enable == 1'b0) || (FHCEn == 1'b0))
     $rose(FHCEn) |-> ##[4:8] (sigs === 0);  
   endproperty: sigs_low_when_harv_set_prop

NOte: If you notice when the FHCEn goes low there is no clock since its gated then i wonder how will the assertion notice this section to evaluate the property, because thats the point where sigs becoming zero… please make me understand this.
If you look at the image its exact prestation of my question, any suggestion thank you ?

3

can any one clarify this doubt ?? please ?

4

I think you need to be more clear in defining the behavior you want to check, for example, looking at the waveform FHCEn and sigs are changing while clk_delayed is disabled which means they are either combinational or they are clocked by another clock—this needs to be clarified too

5

Basically when FHCEn goes 1 then sigs should be 0 as long as FHCEn remains 1 this is the check, but clk_delayed appears exactly as shown in the diagram so this is the trouble