Topics tagged System-Verilog

Topic	Replies	Views	Activity
Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector Coverage Coverage , System-Verilog , Coverage-bins , coverage-bins-uvm-array	2	761	May 17, 2025
Formal Assumption to Model a FIFO Push (with a delay) SystemVerilog assertion , System-Verilog , SVA	3	41	April 29, 2025
Asynchronous FIFO Assertions For Verifying Data Pushed and Popped SystemVerilog SystemVerilog , assertion , System-Verilog , FIFO-UVM-ConstrainedRandom , system-verilog-assertions-past-stable , Assertions-clock	5	802	April 27, 2025
Non-compute-intensive way to add an asynchronous delay to a transaction UVM SystemVerilog , UVM , System-Verilog , driver , uvm_sequence	1	26	April 25, 2025
Assertion on gated clock and after some time ungated clock SystemVerilog assertion , System-Verilog , SVA , Assertion-system-verilog , Assertion-property	3	95	April 10, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	45	March 23, 2025
How to achieve fork-join_none and fork join_any functionality using fork-join SystemVerilog SystemVerilog , System-Verilog , fork-join_any , fork-join_none , fork-join , threads	6	1132	March 12, 2025
How to code the dist statement with array in the constraint SystemVerilog SystemVerilog , System-Verilog	10	1388	March 6, 2025
Pattern Detector 10110 in SV (no FSM) SystemVerilog SystemVerilog , testbench , System-Verilog , SV , queue , systemverilog-Arrays , queues-systemverilog	1	174	February 19, 2025
Functional Coverage as Toggle Coverage Coverage SystemVerilog , Coverage , System-Verilog	3	117	February 17, 2025
I want put value in specific bit slice UVM SystemVerilog , UVM , System-Verilog , SVA	1	48	February 17, 2025
Valid Data Filter SystemVerilog SystemVerilog , System-Verilog , constraint , constraint-randomization , Verilog , constraints , systemverilog-constraint	2	105	February 16, 2025
Scoreboard logic SystemVerilog System-Verilog	8	136	February 10, 2025
Need help in coding an assertion SystemVerilog assertion , System-Verilog , SVA	6	147	January 16, 2025
Mixed packed and unpacked array SystemVerilog SystemVerilog , System-Verilog	3	3934	December 5, 2024
Requirement to initialize dynamic variables within property/sequence SystemVerilog assertion , System-Verilog , SVA	3	425	November 25, 2024
SVA Assertions using only $realtime and nested implications SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	4	172	September 30, 2024
Blocking or non-blocking statement (= vs. <=) SystemVerilog SystemVerilog , System-Verilog , assignment	8	1392	August 10, 2024
Using sequence_item X in agent Y SystemVerilog SystemVerilog , UVM , System-Verilog	2	118	July 30, 2024
What happens to threads that don't finish UVM UVM , System-Verilog , for-loop-fork-join_none , FIFO-UVM-ConstrainedRandom	4	526	July 4, 2024
4 phase req ack SystemVerilog SystemVerilog , UVM , assertion , System-Verilog	10	285	June 7, 2024
Macro to read register fields using RAL Coverage UVM , Coverage , assertion , RAL , System-Verilog	1	316	March 26, 2024
Need assistance with parameterized sequence SystemVerilog assertion , System-Verilog , SVA	1	350	January 6, 2024
Assertion : Assume writing SystemVerilog assertion , System-Verilog	2	250	March 14, 2024
Strong and #-# of SVA SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	7	984	March 12, 2024
Assertion Question SystemVerilog SystemVerilog , assertion , System-Verilog	3	258	March 6, 2024
Implement Clock in Program Block SystemVerilog SystemVerilog , System-Verilog	2	261	February 28, 2024
Variable Delay or Repetition with "until/until_with" SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	3	491	February 28, 2024
Variable Repetition with "intersect" and [->1] doesn't work SystemVerilog SystemVerilog , assertion , System-Verilog , SVA	3	314	February 25, 2024
Use of an Associative array or Queue in System Verilog Assertion Property SystemVerilog SystemVerilog , UVM , assertion , System-Verilog , queue , property , accessing-the-associative-array-elements	6	434	February 23, 2024

Write coverage (Add ignore bin) for a 64 bit vector where the only legal values are when all the 1's are continuous. It is allowed to have 0's at either end of the vector, but there cannot be any 0's between 1's in the vector

Coverage

2

761

May 17, 2025

Formal Assumption to Model a FIFO Push (with a delay)

SystemVerilog

assertion , System-Verilog , SVA

3

41

April 29, 2025

Asynchronous FIFO Assertions For Verifying Data Pushed and Popped

SystemVerilog

SystemVerilog , assertion , System-Verilog , FIFO-UVM-ConstrainedRandom , system-verilog-assertions-past-stable , Assertions-clock

5

802

April 27, 2025

Non-compute-intensive way to add an asynchronous delay to a transaction

UVM

SystemVerilog , UVM , System-Verilog , driver , uvm_sequence

1

26

April 25, 2025

Assertion on gated clock and after some time ungated clock

SystemVerilog

assertion , System-Verilog , SVA , Assertion-system-verilog , Assertion-property

3

95

April 10, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure