Scoreboard logic

SystemVerilog
1

Im trying to develop a scoreboard for memory controller verification. I can compare and verify the read and write operation in scoreboard. Apart from these write and read operations, TB can drive certain commands such as refresh,precharge,mode register to the controller. the controller should issue these commands to the memory model .Memory model will accept these commands and will perform operation. But in scoreboard, how can I verify that the command driven from TB to DUT and the commands issued from DUT to memory model are the same?

2

Could you please explain your question in some more detail, which kind of memory you have etc.
A couple of years ago I was creating a UVM verification environment for DDR -Rams. Is this something like you want to do?

3

This is difficult to answer without more information. Usually one is more concerned with the results of the commands than the commands themselves.

4

Hi
Thanks for the response
I will clear the scenario.

  • Im working on a DDR5 controller verification.
    -I’ve AXI interface for write -read operations and APB interface for commands.
    -Im using an encrypted memory model from vendor for verification of controller.
    -For write read operation i will use axi read data and axi write data in scoreboard and compare it -But in order to verify command operation, if i give any commands through apb interface using pwdata and paddr to the registers configured inside DUT , the controller will issue same commands through dedicated Command Address pins to the memory model and memory model will perform the operation.
    -For eg. refresh command, precharge command etc. But If I want to verify these commands I can see the transcript or I can observe the waveform. Now my doubt is

  1. Apart from that can I implement any method using scoreboard which compares the requested commands from APB interface and issued commands from memory controller??

  2. ⁠How can I implement both APB axi AXI transactions in a single test? such as I need to write a test which will isssue refresh command in between read operations??
    Im using SV testbench

5

Yes.
As I’m working on verification, I want to compare these commands in scoreboard.
Or usually verification team is also concerned with the results only?

6

For your command interface I’d not use a scoreboard. You can compare your data directly in the sequence while using an associative array. What do you want to verify on your data interface. I believe you can simply check a few data written to your DDR5 to indicate it is working in principle. A complete check of all your storage places is impossible due to the size of your memory.

7

Hi NeethuPilakkal,

It would help if you could add a drawing:

  1. The DUT your are trying to verify.
  2. Which verification collaterals (for example: verification agents you are using internal or 3rd party VIPs).
  3. The interfaces between the RTL block(s) and your verification agents.

As soon you will draw this diagram, it would help you to understand better which:
a. Inputs/outputs/flows you have and what stimuli to exercise.
b. What reference-model/s to write.
c. Which Score-boarding techniques to use.

It will help as well other people to help you.

8

Sorry . It was my reply to another post.
For this post, verification architecture is still under construction.

  • Im using SV for verification
  • Verifying DDR5 memory controller
  • Planning to use DDR5 memory model from Micron
  • Have an AXI interface for sending data and address during write/read
  • Have an APB interface for sending commands.
    -Commands will be send from from APB interface and controller will decode those and generate corresponding commands as per spec and will send to memory model.
    -Similarly AXI interface will send data and address to controller.Controller will decode and generate corresponding address and data for memory model.
    I need to develop a verification environment
9

You mentioned you have AXI and APB interfaces, but in the drawing you provided only AHB protocol interface… Am I missing anything?

Is there “an encrypted memory model from vendor” connected to the memory controller, which does not appear in the your drawing?

Adding a link to a video recording from YouTube, by Francois Creasier on advanced scoreboard techniques:

It might help you to clarify few questions and doubts you have, it has good examples and block diagrams…