Topics tagged UVM-RAL-systemverilog-ralmodelling

Topic	Replies	Views	Activity
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	52	March 23, 2025
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	312	December 29, 2023
Comparison of RAL write and read data, i am doing a simple write and simple read, how/where can i compare, this data along with address and some of my registers fields are combination of R,W,RW,RMW..etc.., UVM UVM , UVM-RAL-systemverilog-ralmodelling , RAL-Scoreboard	1	466	October 30, 2023
Problem in ral modelling for certain scenario UVM UVM , uvm-ral , UVM_BACKDOOR , UVM-RAL-systemverilog-ralmodelling , User-defined-frontdoor-VS-UVM_FRONTDOOR , ral_model	0	381	February 25, 2023
Access UVM Register Model organized in pages UVM UVM , UVM-RAL-systemverilog-ralmodelling	0	561	April 4, 2022
How to access fields in encrypted UVM reg model UVM UVM , uvm_reg , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	2	641	February 11, 2022
Is there any scripts to generate the UVM_RAL using ralgen? UVM UVM , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , RAL-efficient	1	989	January 10, 2022
Does anyone have basic example of IPXACT IEEE Xml format for dual bus access? UVM UVM , UVM-RAL-systemverilog-ralmodelling	0	608	September 10, 2021
Instantiating multiple uvm_reg_blocks inside top_env UVM UVM , UVM-RAL-systemverilog-ralmodelling	1	781	August 2, 2021
How to switch between RTL and GATE LEVEL paths wihtout updating build block/register model? UVM UVM , UVM-RAL-systemverilog-ralmodelling	4	1004	June 2, 2021
UVM RAL access type UVM UVM , UVM-RAL-systemverilog-ralmodelling	4	1660	May 21, 2021
Any open source script to generate UVM RAL Model From IPXACT register input? UVM UVM , UVM-RAL-systemverilog-ralmodelling	0	1497	March 5, 2021
Check one register in each block using RAL UVM UVM , UVM-RAL-systemverilog-ralmodelling	1	684	March 4, 2021
Register Modeling UVM UVM , uvm-ral , uvm-backdoor-register-model , UVM-RAL-systemverilog-ralmodelling	10	1814	November 23, 2020
Read Method in UVM RAL UVM UVM , UVM-RAL-systemverilog-ralmodelling	3	2315	November 8, 2020
RAL MODELLING Registers UVM UVM , UVM-RAL-systemverilog-ralmodelling	0	908	August 7, 2020

I cannot find any implementations of a class that extends uvm_reg_file

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure

1

52

March 23, 2025

In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor?

UVM

UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM

0

312

December 29, 2023

Comparison of RAL write and read data, i am doing a simple write and simple read, how/where can i compare, this data along with address and some of my registers fields are combination of R,W,RW,RMW..etc..,

UVM

UVM , UVM-RAL-systemverilog-ralmodelling , RAL-Scoreboard

1

466

October 30, 2023

Problem in ral modelling for certain scenario

UVM

UVM , uvm-ral , UVM_BACKDOOR , UVM-RAL-systemverilog-ralmodelling , User-defined-frontdoor-VS-UVM_FRONTDOOR , ral_model

0

381

February 25, 2023

Access UVM Register Model organized in pages

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

0

561

April 4, 2022

How to access fields in encrypted UVM reg model

UVM

UVM , uvm_reg , UVM-RAL-systemverilog-ralmodelling , RAL-UVM

2

641

February 11, 2022

Is there any scripts to generate the UVM_RAL using ralgen?

UVM

UVM , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , RAL-efficient

1

989

January 10, 2022

Does anyone have basic example of IPXACT IEEE Xml format for dual bus access?

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

0

608

September 10, 2021

Instantiating multiple uvm_reg_blocks inside top_env

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

1

781

August 2, 2021

How to switch between RTL and GATE LEVEL paths wihtout updating build block/register model?

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

4

1004

June 2, 2021

UVM RAL access type

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

4

1660

May 21, 2021

Any open source script to generate UVM RAL Model From IPXACT register input?

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

0

1497

March 5, 2021

Check one register in each block using RAL

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

1

684

March 4, 2021

Register Modeling

UVM

UVM , uvm-ral , uvm-backdoor-register-model , UVM-RAL-systemverilog-ralmodelling

10

1814

November 23, 2020

Read Method in UVM RAL

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

3

2315

November 8, 2020

RAL MODELLING Registers

UVM

UVM , UVM-RAL-systemverilog-ralmodelling

0

908

August 7, 2020