I have a scenario where write/read happens to certain registers with single address. From firmware also, it is a single 32bit variable. Only RTL does different assignments from each slices.
VHDL RTL register updating logic :-
if address == 'h my_addr:
rtl_mod.a ← data[0] , rtl_mod.b ← data[1:3] ,rtl_mod.c ← data[4:16] , rtl_mod.d ← data[17:31]…
//for read, data[0] ← rtl_mod.a,…
if address == 'h other_addr1:
rtl_mod.other_reg1 ← data;
if address == 'h other_addr2:
rtl_mod.other_reg2 ← data;
RAL MODEL:-
I am keeping 1 reg for all rtl.a,rtl.b,.(assuming each reg has unique address).
class xyz extends uvm_reg;
uvm_reg_field a;
uvm_reg_field b;
…
is there any fundamental issues in my approach.?
[PROBLEMS]
FRONTDOOR:
If i do xyz_reg.a.write(…) // here a will be updated but other values will remain as previous. [Expected behavior: all other b, c, d should be ‘0’] is there any possibility to model this, other than hard work around.
WORKAROUND:- I am able to do frontdoor write to that register as a whole to my_addr.(i should manually take care of every other bit to set to zeros) is it safe to go this way?
BACKDOOR :
I am not sure how to assign different RTL paths to each fields (for backdoor).
As for xyz_reg, i need to concatenate {rtl_mod.a , rtl_mod.b , rtl_mod.c , rtl_mod.d}
Is there any way if we could assign concatenation of RTL paths based on index to a reg .?