Topics tagged uvm-ral

Topic	Replies	Views	Activity
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	2	67	October 27, 2024
UVM RAL: Check on read issue UVM Mirrored-values-and-desired-values-in-UVM-RAL , uvm_reg , uvm-ral	0	83	September 23, 2024
# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq UVM uvm-ral	1	108	August 21, 2024
Uvm_path_e vs uvm_door_e UVM SystemVerilog , UVM , uvm-ral	2	92	July 26, 2024
UVM register model UVM RAL , uvm-ral	0	105	July 1, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM UVM , uvm-ral , Ral-write-and-read-methhods	4	3364	June 28, 2024
Issue with RAL Coverage bins creation UVM UVM , uvm-ral , ral_coverage	3	233	May 16, 2024
Providing the RAL with protocol layer implemented with virtual sequence/sequencer UVM virtual-sequencer , uvm-ral	1	176	March 18, 2024
UVM RAL: Can we always use backdoor access instead of frontdoor access? UVM UVM , uvm-ral , UVM-RAL-back-door-peek	2	863	March 9, 2024
UVM Adapter for Pipelined protocols like AHB, AXI etc UVM uvm_reg_adapter , uvm-ral , axi , AHB , Register-model	0	255	February 24, 2024
Virtual registers and uvm_mem examples UVM uvm_mem , uvm-ral	0	202	February 6, 2024
What is backtracking in brief and how we do that ? UVM UVM , SV , uvm-ral	1	232	December 29, 2023
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	292	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	287	December 27, 2023
Mirrored Value is not getting updated for second reg model's write/read calls UVM SystemVerilog , UVM , uvm_reg , uvm-ral , mirrored-value , Calling-predict-for-registers	0	432	September 4, 2023
UVM RAL: REG SEQUENCE CLASS UVM UVM , uvm-ral	0	237	August 30, 2023
UVM reg atomicity for write/read tasks UVM UVM , uvm-ral	5	2674	July 16, 2023
How to read all the register in RAL model using reg_map? UVM UVM , uvm-ral	4	3594	July 5, 2023
UVM Ral Indirect Access UVM UVM , uvm-ral , indirect-access	0	417	May 18, 2023
Problem in ral modelling for certain scenario UVM UVM , uvm-ral , UVM_BACKDOOR , UVM-RAL-systemverilog-ralmodelling , User-defined-frontdoor-VS-UVM_FRONTDOOR , ral_model	0	370	February 25, 2023
How to get the RAL model handle in Scoreboard UVM UVM , uvm-ral , register-status-check , RAL-in-scoreboard	2	1157	December 22, 2022
Re-lock RAL model UVM UVM , uvm-ral	0	512	September 20, 2022
Can I use ">>" on the configure function in RAL model? UVM UVM , uvm-ral	3	590	July 4, 2022
RAL Model Doubts UVM UVM , uvm-ral	15	3275	April 7, 2022
Communication between predictor and RAL model UVM UVM , uvm-ral	0	708	October 27, 2021
Post_predict callback getting call twice in case reg sequence UVM SystemVerilog , UVM , RAL-register-UVM , uvm-ral	1	957	September 27, 2021
[RAL] Monitoring write and read transactions with a protocol that works in two cycles UVM UVM , uvm-ral	1	1162	July 27, 2021
Does get_reg_by_offset provide the register link if used at the top level reg_map? UVM UVM , uvm-ral	0	610	June 2, 2021
VHDL Slicing in RAL Backdoor Paths - Possible? UVM UVM , uvm-ral , Backdoor_access-HDL-access-methods	1	893	May 18, 2021
Uvm_backdoor and uvm_frontdoor parallel access to a register UVM UVM , uvm-ral	5	2438	March 27, 2021