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Virtual Register
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1
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29
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December 10, 2025
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Reg_block.get_reg_by_name returns unexpected null
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0
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36
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July 30, 2025
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Memory Verification without RAL
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1
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100
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May 27, 2025
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Doubt in create_map in uvm_ral
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1
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44
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May 9, 2025
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UVM RAL model for register and memory with overlapping address and accessing them using the same interface
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4
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184
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March 27, 2025
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I cannot find any implementations of a class that extends uvm_reg_file
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1
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69
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March 23, 2025
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UVM RAL: Mapping Same Register Block to Two Address Ranges
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0
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59
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March 12, 2025
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Coverage for volatile registers in UVM RAL
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3
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132
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March 6, 2025
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Implementing Outstanding AXI transactions using RAL
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1
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244
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December 19, 2024
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Advantage of calling set() over write()
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1
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388
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October 20, 2024
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UVM RAL: Check on read issue
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0
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197
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September 23, 2024
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# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq
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1
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324
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August 21, 2024
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Uvm_path_e vs uvm_door_e
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2
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170
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July 26, 2024
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UVM register model
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0
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148
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July 1, 2024
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Why does the RAL read() update the mirrored AND desired register model values?
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4
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3816
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June 28, 2024
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Issue with RAL Coverage bins creation
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3
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307
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May 16, 2024
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Providing the RAL with protocol layer implemented with virtual sequence/sequencer
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1
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211
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March 18, 2024
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UVM RAL: Can we always use backdoor access instead of frontdoor access?
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2
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1090
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March 9, 2024
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UVM Adapter for Pipelined protocols like AHB, AXI etc
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0
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382
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February 24, 2024
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Virtual registers and uvm_mem examples
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0
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234
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February 6, 2024
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What is backtracking in brief and how we do that ?
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1
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253
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December 29, 2023
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In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor?
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0
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318
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December 29, 2023
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Access (to W/R) 2 Specific fields in a 32-bit register
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1
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334
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December 27, 2023
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Mirrored Value is not getting updated for second reg model's write/read calls
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0
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506
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September 4, 2023
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UVM RAL: REG SEQUENCE CLASS
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0
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248
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August 30, 2023
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UVM reg atomicity for write/read tasks
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5
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2848
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July 16, 2023
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How to read all the register in RAL model using reg_map?
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4
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3824
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July 5, 2023
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UVM Ral Indirect Access
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0
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442
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May 18, 2023
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Problem in ral modelling for certain scenario
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0
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387
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February 25, 2023
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How to get the RAL model handle in Scoreboard
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2
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1416
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December 22, 2022
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