Topics tagged uvm-ral

Topic	Replies	Views	Activity
Virtual Register UVM RAL , uvm-ral , RAL-UVM	1	29	December 10, 2025
Reg_block.get_reg_by_name returns unexpected null UVM RAL , uvm-ral , RAL-UVM	0	36	July 30, 2025
Memory Verification without RAL UVM uvm-ral , Debug	1	100	May 27, 2025
Doubt in create_map in uvm_ral UVM uvm-ral	1	44	May 9, 2025
UVM RAL model for register and memory with overlapping address and accessing them using the same interface UVM RAL , RAL-register-UVM , uvm-ral	4	184	March 27, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	69	March 23, 2025
UVM RAL: Mapping Same Register Block to Two Address Ranges UVM RAL , uvm-ral	0	59	March 12, 2025
Coverage for volatile registers in UVM RAL UVM UVM , Coverage , RAL , uvm-ral	3	132	March 6, 2025
Implementing Outstanding AXI transactions using RAL UVM UVM , RAL , uvm-ral	1	244	December 19, 2024
Advantage of calling set() over write() UVM UVM , RAL , uvm-ral	1	388	October 20, 2024
UVM RAL: Check on read issue UVM Mirrored-values-and-desired-values-in-UVM-RAL , uvm_reg , uvm-ral	0	197	September 23, 2024
# UVM_FATAL @ 0: reporter@@default_parent_seq [SEQ] neither the item's sequencer nor dedicated sequencer has been supplied to start item in default_parent_seq UVM uvm-ral	1	324	August 21, 2024
Uvm_path_e vs uvm_door_e UVM SystemVerilog , UVM , uvm-ral	2	170	July 26, 2024
UVM register model UVM RAL , uvm-ral	0	148	July 1, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM UVM , uvm-ral , Ral-write-and-read-methhods	4	3816	June 28, 2024
Issue with RAL Coverage bins creation UVM UVM , uvm-ral , ral_coverage	3	307	May 16, 2024
Providing the RAL with protocol layer implemented with virtual sequence/sequencer UVM virtual-sequencer , uvm-ral	1	211	March 18, 2024
UVM RAL: Can we always use backdoor access instead of frontdoor access? UVM UVM , uvm-ral , UVM-RAL-back-door-peek	2	1090	March 9, 2024
UVM Adapter for Pipelined protocols like AHB, AXI etc UVM uvm_reg_adapter , uvm-ral , axi , AHB , Register-model	0	382	February 24, 2024
Virtual registers and uvm_mem examples UVM uvm_mem , uvm-ral	0	234	February 6, 2024
What is backtracking in brief and how we do that ? UVM UVM , SV , uvm-ral	1	253	December 29, 2023
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	318	December 29, 2023
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	334	December 27, 2023
Mirrored Value is not getting updated for second reg model's write/read calls UVM SystemVerilog , UVM , uvm_reg , uvm-ral , mirrored-value , Calling-predict-for-registers	0	506	September 4, 2023
UVM RAL: REG SEQUENCE CLASS UVM UVM , uvm-ral	0	248	August 30, 2023
UVM reg atomicity for write/read tasks UVM UVM , uvm-ral	5	2848	July 16, 2023
How to read all the register in RAL model using reg_map? UVM UVM , uvm-ral	4	3824	July 5, 2023
UVM Ral Indirect Access UVM UVM , uvm-ral , indirect-access	0	442	May 18, 2023
Problem in ral modelling for certain scenario UVM UVM , uvm-ral , UVM_BACKDOOR , UVM-RAL-systemverilog-ralmodelling , User-defined-frontdoor-VS-UVM_FRONTDOOR , ral_model	0	387	February 25, 2023
How to get the RAL model handle in Scoreboard UVM UVM , uvm-ral , register-status-check , RAL-in-scoreboard	2	1416	December 22, 2022

Virtual Register

UVM

RAL , uvm-ral , RAL-UVM

1

29

December 10, 2025

Reg_block.get_reg_by_name returns unexpected null

UVM

RAL , uvm-ral , RAL-UVM

0

36

July 30, 2025

Memory Verification without RAL

UVM

uvm-ral , Debug

1

100

May 27, 2025

Doubt in create_map in uvm_ral

UVM

uvm-ral

1

44

May 9, 2025

UVM RAL model for register and memory with overlapping address and accessing them using the same interface

UVM

RAL , RAL-register-UVM , uvm-ral

4

184

March 27, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure