Providing the RAL with protocol layer implemented with virtual sequence/sequencer
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1
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56
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March 18, 2024
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UVM RAL: Can we always use backdoor access instead of frontdoor access?
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2
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564
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March 9, 2024
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UVM Adapter for Pipelined protocols like AHB, AXI etc
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0
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102
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February 24, 2024
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Virtual registers and uvm_mem examples
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0
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81
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February 6, 2024
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What is backtracking in brief and how we do that ?
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1
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112
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December 29, 2023
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In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor?
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0
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127
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December 29, 2023
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Access (to W/R) 2 Specific fields in a 32-bit register
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1
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130
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December 27, 2023
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Mirrored Value is not getting updated for second reg model's write/read calls
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0
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206
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September 4, 2023
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UVM RAL: REG SEQUENCE CLASS
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0
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125
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August 30, 2023
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UVM reg atomicity for write/read tasks
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5
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2399
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July 16, 2023
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How to read all the register in RAL model using reg_map?
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4
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3227
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July 5, 2023
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UVM Ral Indirect Access
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0
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297
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May 18, 2023
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Problem in ral modelling for certain scenario
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0
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282
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February 25, 2023
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How to get the RAL model handle in Scoreboard
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2
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881
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December 22, 2022
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Re-lock RAL model
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0
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349
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September 20, 2022
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Can I use ">>" on the configure function in RAL model?
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3
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449
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July 4, 2022
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RAL Model Doubts
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15
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3005
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April 7, 2022
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Communication between predictor and RAL model
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0
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614
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October 27, 2021
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Post_predict callback getting call twice in case reg sequence
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1
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797
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September 27, 2021
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[RAL] Monitoring write and read transactions with a protocol that works in two cycles
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1
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1025
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July 27, 2021
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Does get_reg_by_offset provide the register link if used at the top level reg_map?
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0
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495
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June 2, 2021
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VHDL Slicing in RAL Backdoor Paths - Possible?
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1
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766
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May 18, 2021
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Uvm_backdoor and uvm_frontdoor parallel access to a register
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5
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2118
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March 27, 2021
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Reuse constraints in child classes
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1
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883
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February 15, 2021
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RAL Model register field read/write
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1
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1935
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February 10, 2021
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Register Modeling
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10
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1540
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November 23, 2020
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Where to place sample_values() for getting coverage in UVM RAL?
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3
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1490
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November 17, 2020
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UVM RAL on two different interfaces in the system
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0
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855
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October 19, 2020
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Why does the RAL read() update the mirrored AND desired register model values?
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2
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2926
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June 24, 2020
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Uvm_reg_indirect_data
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1
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785
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May 11, 2020
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