Making Testbench Emulation friendly
|
|
1
|
119
|
June 20, 2024
|
Triggering SV event as part of sequence expression
|
|
3
|
119
|
June 10, 2024
|
What is backtracking in brief and how we do that ?
|
|
1
|
199
|
December 29, 2023
|
How to declare queue fo queue, each queue is struct element
|
|
1
|
410
|
September 16, 2023
|
SystemVerilog Union
|
|
1
|
269
|
August 25, 2023
|
Integrating multiple VIPS with single DUT
|
|
7
|
4882
|
July 24, 2023
|
Getting Clock period Mismatch Error while comparing two clocks even though values of two clocks are same
|
|
3
|
607
|
May 17, 2023
|
Race condition while sampling a covergroup
|
|
4
|
770
|
April 15, 2023
|
If error comes then test will displayed as pass
|
|
4
|
792
|
October 27, 2022
|
NULL pointer dereference
|
|
4
|
2523
|
April 21, 2022
|
Mailbox
|
|
3
|
750
|
April 12, 2022
|
How to verify if two bits of a 32 bit register are swapped?
|
|
10
|
2135
|
August 21, 2021
|
How to take input from the transcript in Questasim or generally in any other Tool using verilog / Systemverilog / UVM?
|
|
2
|
995
|
June 24, 2020
|
Do we have any other method to achieve FORCE and RELEASE
|
|
1
|
687
|
April 13, 2020
|
Error with SV Interface wrapper for Verilog DUT
|
|
8
|
5695
|
March 24, 2020
|
Wait statement code optimization
|
|
2
|
813
|
January 13, 2020
|
When master signal is asserted a slave signal should be asserted after some time delay. the assertion is not failing if the duration is more
|
|
4
|
1824
|
September 20, 2019
|
Can I Dump perticular protocol singnal using wildcard (*)? How can I Dump input,inout, output signals only?
|
|
2
|
1303
|
July 11, 2019
|
About concurrent assertion in FSM
|
|
3
|
1818
|
July 23, 2018
|
OOPS terminologies in SV
|
|
2
|
2295
|
January 7, 2018
|
Multiple inheritence in SV
|
|
2
|
2338
|
January 2, 2018
|
Factory objects and components are virtual?
|
|
1
|
1353
|
September 17, 2017
|
VHDL module verification
|
|
2
|
1692
|
August 29, 2017
|
How to change value of the variable which we have given the value using `define?
|
|
4
|
2251
|
April 27, 2017
|
Array of constraints challenge
|
|
5
|
2116
|
February 22, 2017
|
Giving equal weight to all bins across all functional cover groups
|
|
1
|
1380
|
November 22, 2016
|
Projects/project ideas for learning SV verification
|
|
1
|
4666
|
September 20, 2016
|
Usage of bind statement with VHDL DUT
|
|
5
|
8738
|
November 18, 2015
|
Same property name in both base and derived class in System verilog
|
|
1
|
3415
|
July 14, 2015
|
Fatal errors in system verilog
|
|
4
|
5386
|
May 28, 2015
|