Race condition while sampling a covergroup

SystemVerilog
, , ,
1

I have faced some issues related to cover point coverage. Following is the structure of the cover point I am trying to cover -

Let’s say there are 4 signals in the cover point i.e.{A,B,C,D} where A is a 4-bit vector, B is one 2-bit and C & D are one-bit each, and the following transition bin is written -

 wildcard bins BIN_1 = ({8'b1100_11_1_1}=>{8'b1100_00_0_1}=>{8'b1100_00_0_0})

Sampling information: cover group is being sampled at all the signals present inside this coverpoint

behavior of A,B,C,D :

in above written BIN_1 definition, when the first condition is true and the simulator proceeds to check for the second transition i.e. 8’b1100_00_0_1 then here signal B & C are changing at the same time i.e. C is a kind of reset which triggers B to ‘00’ when reset C is asserted to ‘0’. so In a way, I can see these transitions happening on Waveform, but the cover bin is not getting hit. Can you please help me understand it?

I tried to even observe a few things to hit this coverbin :

  1. expanded time step for the second transition & I could see some delta cycle delays, in signals B going ‘00’ & C going ‘0’, which can cause covergroup to sample multiple times in the same time step. SO I tried the following option i.e. type_option.strobe = 1 in cover group to sample it only once in the postponed region. But this is also not working
  2. I tried to replace the second transition definition as
    a) {8’b1100_??0_1}
    b) {8’b1100_00    ?1}
    c) {8’b1100_11    ?1}
    d) {8’b1100_11_0_1}
    e) {8’b1100    ??_?_1}

but none of them is working.

Can you please help me with how to cover it??

Regards
Abhinay

2

In reply to oasis_abhi:

type_option.strobe = 1 should have worked. You show us an example of how you are sampling the covergroup, and a testbench the recreates the data you are trying to sample.

3

In reply to dave_59:

Thanks a lot, Dev for the reply. Let me quote the exact cover group code and trigger event which I am using in my TB :

The bin I am concerned about is below, present inside the first cover point named cp_PG_EXIT_CASES i.e.
wildcard bins P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN1
wildcard bins P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN2
wildcard bins P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN3
wildcard bins P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN4

**And here for the concerned bins which I have written above, I can see on the waveform, no other signal (present inside vector sample1 or sample2 i.e. the signals on which covergroup triggers) is changing in b/w change of signals on which the transition bin is written. Thus it also rules out any possibility of false coverage or miss-sampling or something.
**

covergroup pg_exit_cg(string name) with function sample (int en, logic[18:0] sample1, logic [16:0] sample2);

option.per_instance = 1;
option.name = name;
type_option.strobe = 1;

cp_PG_EXIT_CASES : coverpoint sample1 iff (en && m_ctrl_vif.pipe_laneX_protocol==0) {
wildcard bins P1_2_MPLLA_FORCE_EN_GEN3 = ({19’b1100_00_??1_0_0_0010_1_1_00}=>{19’b1100_00??1_1_0_0010_1?00}=>{19’b1100_00??1_1_0_0010_1_0_00});
wildcard bins P1_2_SIDEBAND_MPLLA_FORCE_EN_GEN3 = ({19’b0100_11??1_0_0_0010_1_1_00}=>{19’b0100_11??1_1_0_0010_1?00}=>{19’b0100_11??1_1_0_0010_1_0_00});
wildcard bins P2_NOBEACON_MPLLA_FORCE_EN_GEN3 = ({19’b1111_00??1_0_0_0010_1_1_00}=>{19’b1111_00??1_1_0_0010_1?00}=>{19’b1111_00??1_1_0_0010_1_0_00});
wildcard bins P1_2_MPLLA_FORCE_EN_GEN4 = ({19’b1100_00??1_0_0_0011_1_1_00}=>{19’b1100_00??1_1_0_0011_1?00}=>{19’b1100_00??1_1_0_0011_1_0_00});
wildcard bins P1_2_SIDEBAND_MPLLA_FORCE_EN_GEN4 = ({19’b0100_11??1_0_0_0011_1_1_00}=>{19’b0100_11??1_1_0_0011_1?00}=>{19’b0100_11??1_1_0_0011_1_0_00});
wildcard bins P2_NOBEACON_MPLLA_FORCE_EN_GEN4 = ({19’b1111_00??1_0_0_0011_1_1_00}=>{19’b1111_00??1_1_0_0011_1?00}=>{19’b1111_00??_1_1_0_0011_1_0_00});

wildcard bins  P1_2_MPLLB_FORCE_EN_GEN1                           = ({19'b1100_00_?_?_1_0_0_0000_1_1_00}=>{19'b1100_00_?_?_1_0_1_0000_1_?_00}=>{19'b1100_00_?_?_1_0_1_0000_1_0_00});

wildcard bins P1_2_SIDEBAND_MPLLB_FORCE_EN_GEN1 = ({19’b0100_11_??1_0_0_0000_1_1_00}=>{19’b0100_11??1_0_1_0000_1?00}=>{19’b0100_11??1_0_1_0000_1_0_00});
wildcard bins P2_NOBEACON_MPLLB_FORCE_EN_GEN1 = ({19’b1111_00??1_0_0_0000_1_1_00}=>{19’b1111_00??1_0_1_0000_1?00}=>{19’b1111_00??1_0_1_0000_1_0_00});
wildcard bins P1_2_MPLLB_FORCE_EN_GEN2 = ({19’b1100_00??1_0_0_0001_1_1_00}=>{19’b1100_00??1_0_1_0001_1?00}=>{19’b1100_00??1_0_1_0001_1_0_00});
wildcard bins P1_2_SIDEBAND_MPLLB_FORCE_EN_GEN2 = ({19’b0100_11??1_0_0_0001_1_1_00}=>{19’b0100_11??1_0_1_0001_1?00}=>{19’b0100_11??1_0_1_0001_1_0_00});
wildcard bins P2_NOBEACON_MPLLB_FORCE_EN_GEN2 = ({19’b1111_00??1_0_0_0001_1_1_00}=>{19’b1111_00??1_0_1_0001_1?00}=>{19’b1111_00?_?_1_0_1_0001_1_0_00});

wildcard bins  P1_2_CONFIG_BIT9_LANE_RESET_GEN1                   = ({19'b1100_00_0_?_1_0_0_0000_1_1_00}=>{19'b1100_00_0_?_0_0_0_0000_1_?_00}=>{19'b1100_00_0_?_0_0_0_0000_1_0_00});
wildcard bins  P1_2_CONFIG_BIT6_PG_MODE_GEN1                      = ({19'b1100_00_?_0_1_0_0_0000_1_1_00}=>{19'b1100_00_?_0_1_0_0_0000_0_?_00}=>{19'b1100_00_?_0_1_0_0_0000_0_0_00});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_01_GEN1                 = ({19'b1100_00_?_?_1_0_0_0000_1_1_00}=>{19'b1100_00_?_?_1_0_0_0000_1_?_01}=>{19'b1100_00_?_?_1_0_0_0000_1_0_01});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_11_GEN1                 = ({19'b1100_00_?_?_1_0_0_0000_1_1_00}=>{19'b1100_00_?_?_1_0_0_0000_1_?_11}=>{19'b1100_00_?_?_1_0_0_0000_1_0_11});
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN1          = ({19'b0100_11_0_?_1_0_0_0000_1_1_00}=>{19'b0100_00_0_?_0_0_0_0000_1_1_00}=>{19'b0100_00_0_?_0_0_0_0000_1_0_00});  // Race
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT6_PG_MODE_GEN1             = ({19'b0100_11_?_0_1_0_0_0000_1_1_00}=>{19'b0100_11_?_0_1_0_0_0000_0_?_00}=>{19'b0100_11_?_0_1_0_0_0000_0_0_00});
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_01_GEN1        = ({19'b0100_11_?_?_1_0_0_0000_1_1_00}=>{19'b0100_11_?_?_1_0_0_0000_1_?_01}=>{19'b0100_00_?_?_1_0_0_0000_1_0_01});  // Race
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_11_GEN1        = ({19'b0100_11_?_?_1_0_0_0000_1_1_00}=>{19'b0100_11_?_?_1_0_0_0000_1_?_11}=>{19'b0100_11_?_?_1_0_0_0000_1_0_11});
wildcard bins  P2_NOBEACON_CONFIG_BIT9_LANE_RESET_GEN1            = ({19'b1111_00_0_?_1_0_0_0000_1_1_00}=>{19'b1111_00_0_?_0_0_0_0000_1_?_00}=>{19'b1111_00_0_?_0_0_0_0000_1_0_00});
wildcard bins  P2_NOBEACON_CONFIG_BIT6_PG_MODE_GEN1               = ({19'b1111_00_?_0_1_0_0_0000_1_1_00}=>{19'b1111_00_?_0_1_0_0_0000_0_?_00}=>{19'b1111_00_?_0_1_0_0_0000_0_0_00});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_01_GEN1          = ({19'b1111_00_?_?_1_0_0_0000_1_1_00}=>{19'b1111_00_?_?_1_0_0_0000_1_?_01}=>{19'b1111_00_?_?_1_0_0_0000_1_0_01});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_11_GEN1          = ({19'b1111_00_?_?_1_0_0_0000_1_1_00}=>{19'b1111_00_?_?_1_0_0_0000_1_?_11}=>{19'b1111_00_?_?_1_0_0_0000_1_0_11});

wildcard bins  P1_2_CONFIG_BIT9_LANE_RESET_GEN2                   = ({19'b1100_00_0_?_1_0_0_0001_1_1_00}=>{19'b1100_00_0_?_0_0_0_0001_1_?_00}=>{19'b1100_00_0_?_0_0_0_0001_1_0_00});
wildcard bins  P1_2_CONFIG_BIT6_PG_MODE_GEN2                      = ({19'b1100_00_?_0_1_0_0_0001_1_1_00}=>{19'b1100_00_?_0_1_0_0_0001_0_?_00}=>{19'b1100_00_?_0_1_0_0_0001_0_0_00});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_01_GEN2                 = ({19'b1100_00_?_?_1_0_0_0001_1_1_00}=>{19'b1100_00_?_?_1_0_0_0001_1_?_01}=>{19'b1100_00_?_?_1_0_0_0001_1_0_01});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_11_GEN2                 = ({19'b1100_00_?_?_1_0_0_0001_1_1_00}=>{19'b1100_00_?_?_1_0_0_0001_1_?_11}=>{19'b1100_00_?_?_1_0_0_0001_1_0_11});

wildcard bins P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN2 = ({19’b0100_11_0_?1_0_0_0001_1_1_00}=>{19’b0100_00_0?0_0_0_0001_1_1_00}=>{19’b0100_00_0?0_0_0_0001_1_0_00}); // Race
wildcard bins P1_2_SIDEBAND_CONFIG_BIT6_PG_MODE_GEN2 = ({19’b0100_11?0_1_0_0_0001_1_1_00}=>{19’b0100_11?0_1_0_0_0001_0?00}=>{19’b0100_11?0_1_0_0_0001_0_0_00});
wildcard bins P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_01_GEN2 = ({19’b0100_11??1_0_0_0001_1_1_00}=>{19’b0100_11??1_0_0_0001_1_1_01}=>{19’b0100_00??1_0_0_0001_1_0_01}); // Race
wildcard bins P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_11_GEN2 = ({19’b0100_11??1_0_0_0001_1_1_00}=>{19’b0100_11??1_0_0_0001_1?11}=>{19’b0100_11??1_0_0_0001_1_0_11});
wildcard bins P2_NOBEACON_CONFIG_BIT9_LANE_RESET_GEN2 = ({19’b1111_00_0?1_0_0_0001_1_1_00}=>{19’b1111_00_0?0_0_0_0001_1?00}=>{19’b1111_00_0?0_0_0_0001_1_0_00});
wildcard bins P2_NOBEACON_CONFIG_BIT6_PG_MODE_GEN2 = ({19’b1111_00?0_1_0_0_0001_1_1_00}=>{19’b1111_00?0_1_0_0_0001_0?00}=>{19’b1111_00?0_1_0_0_0001_0_0_00});
wildcard bins P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_01_GEN2 = ({19’b1111_00??1_0_0_0001_1_1_00}=>{19’b1111_00??1_0_0_0001_1?01}=>{19’b1111_00??1_0_0_0001_1_0_01});
wildcard bins P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_11_GEN2 = ({19’b1111_00??1_0_0_0001_1_1_00}=>{19’b1111_00??1_0_0_0001_1?11}=>{19’b1111_00??_1_0_0_0001_1_0_11});

wildcard bins  P1_2_CONFIG_BIT9_LANE_RESET_GEN3                   = ({19'b1100_00_0_?_1_0_0_0010_1_1_00}=>{19'b1100_00_0_?_0_0_0_0010_1_?_00}=>{19'b1100_00_0_?_0_0_0_0010_1_0_00});
wildcard bins  P1_2_CONFIG_BIT6_PG_MODE_GEN3                      = ({19'b1100_00_?_0_1_0_0_0010_1_1_00}=>{19'b1100_00_?_0_1_0_0_0010_0_?_00}=>{19'b1100_00_?_0_1_0_0_0010_0_0_00});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_01_GEN3                 = ({19'b1100_00_?_?_1_0_0_0010_1_1_00}=>{19'b1100_00_?_?_1_0_0_0010_1_?_01}=>{19'b1100_00_?_?_1_0_0_0010_1_0_01});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_11_GEN3                 = ({19'b1100_00_?_?_1_0_0_0010_1_1_00}=>{19'b1100_00_?_?_1_0_0_0010_1_?_11}=>{19'b1100_00_?_?_1_0_0_0010_1_0_11});
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN3          = ({19'b0100_11_0_?_1_0_0_0010_1_1_00}=>{19'b0100_00_0_?_0_0_0_0010_1_?_00}=>{19'b0100_00_0_?_0_0_0_0010_1_0_00});  // Race
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT6_PG_MODE_GEN3             = ({19'b0100_11_?_0_1_0_0_0010_1_1_00}=>{19'b0100_11_?_0_1_0_0_0010_0_?_00}=>{19'b0100_11_?_0_1_0_0_0010_0_0_00});
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_01_GEN3        = ({19'b0100_11_?_?_1_0_0_0010_1_1_00}=>{19'b0100_11_?_?_1_0_0_0010_1_?_01}=>{19'b0100_00_?_?_1_0_0_0010_1_0_01});  // Race
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_11_GEN3        = ({19'b0100_11_?_?_1_0_0_0010_1_1_00}=>{19'b0100_11_?_?_1_0_0_0010_1_?_11}=>{19'b0100_11_?_?_1_0_0_0010_1_0_11});

wildcard bins  P2_NOBEACON_CONFIG_BIT9_LANE_RESET_GEN3            = ({19'b1111_00_0_?_1_0_0_0010_1_1_00}=>{19'b1111_00_0_?_0_0_0_0010_1_?_00}=>{19'b1111_00_0_?_0_0_0_0010_1_0_00});
wildcard bins  P2_NOBEACON_CONFIG_BIT6_PG_MODE_GEN3               = ({19'b1111_00_?_0_1_0_0_0010_1_1_00}=>{19'b1111_00_?_0_1_0_0_0010_0_?_00}=>{19'b1111_00_?_0_1_0_0_0010_0_0_00});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_01_GEN3          = ({19'b1111_00_?_?_1_0_0_0010_1_1_00}=>{19'b1111_00_?_?_1_0_0_0010_1_?_01}=>{19'b1111_00_?_?_1_0_0_0010_1_0_01});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_11_GEN3          = ({19'b1111_00_?_?_1_0_0_0010_1_1_00}=>{19'b1111_00_?_?_1_0_0_0010_1_?_11}=>{19'b1111_00_?_?_1_0_0_0010_1_0_11});

wildcard bins  P1_2_CONFIG_BIT9_LANE_RESET_GEN4                   = ({19'b1100_00_0_?_1_0_0_0011_1_1_00}=>{19'b1100_00_0_?_0_0_0_0011_1_?_00}=>{19'b1100_00_0_?_0_0_0_0011_1_0_00});
wildcard bins  P1_2_CONFIG_BIT6_PG_MODE_GEN4                      = ({19'b1100_00_?_0_1_0_0_0011_1_1_00}=>{19'b1100_00_?_0_1_0_0_0011_0_?_00}=>{19'b1100_00_?_0_1_0_0_0011_0_0_00});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_01_GEN4                 = ({19'b1100_00_?_?_1_0_0_0011_1_1_00}=>{19'b1100_00_?_?_1_0_0_0011_1_?_01}=>{19'b1100_00_?_?_1_0_0_0011_1_0_01});
wildcard bins  P1_2_MAXPCLK_REQ_CHANGE_TO_11_GEN4                 = ({19'b1100_00_?_?_1_0_0_0011_1_1_00}=>{19'b1100_00_?_?_1_0_0_0011_1_?_11}=>{19'b1100_00_?_?_1_0_0_0011_1_0_11});
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT9_LANE_RESET_GEN4          = ({19'b0100_11_0_?_1_0_0_0011_1_1_00}=>{19'b0100_00_0_?_0_0_0_0011_1_?_00}=>{19'b0100_00_0_?_0_0_0_0011_1_0_00});  // Race
wildcard bins  P1_2_SIDEBAND_CONFIG_BIT6_PG_MODE_GEN4             = ({19'b0100_11_?_0_1_0_0_0011_1_1_00}=>{19'b0100_11_?_0_1_0_0_0011_0_?_00}=>{19'b0100_11_?_0_1_0_0_0011_0_0_00});
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_01_GEN4        = ({19'b0100_11_?_?_1_0_0_0011_1_1_00}=>{19'b0100_11_?_?_1_0_0_0011_1_?_01}=>{19'b0100_00_?_?_1_0_0_0011_1_0_01});  // Race
wildcard bins  P1_2_SIDEBAND_MAXPCLK_REQ_CHANGE_TO_11_GEN4        = ({19'b0100_11_?_?_1_0_0_0011_1_1_00}=>{19'b0100_11_?_?_1_0_0_0011_1_?_11}=>{19'b0100_11_?_?_1_0_0_0011_1_0_11});

wildcard bins  P2_NOBEACON_CONFIG_BIT9_LANE_RESET_GEN4            = ({19'b1111_00_0_?_1_0_0_0011_1_1_00}=>{19'b1111_00_0_?_0_0_0_0011_1_?_00}=>{19'b1111_00_0_?_0_0_0_0011_1_0_00});
wildcard bins  P2_NOBEACON_CONFIG_BIT6_PG_MODE_GEN4               = ({19'b1111_00_?_0_1_0_0_0011_1_1_00}=>{19'b1111_00_?_0_1_0_0_0011_0_?_00}=>{19'b1111_00_?_0_1_0_0_0011_0_0_00});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_01_GEN4          = ({19'b1111_00_?_?_1_0_0_0011_1_1_00}=>{19'b1111_00_?_?_1_0_0_0011_1_?_01}=>{19'b1111_00_?_?_1_0_0_0011_1_0_01});
wildcard bins  P2_NOBEACON_MAXPCLK_REQ_CHANGE_TO_11_GEN4          = ({19'b1111_00_?_?_1_0_0_0011_1_1_00}=>{19'b1111_00_?_?_1_0_0_0011_1_?_11}=>{19'b1111_00_?_?_1_0_0_0011_1_0_11});

}

cp_LANE_DISABLE : coverpoint sample2 iff (en && m_ctrl_vif.pipe_laneX_protocol==0) {
wildcard bins LANE_ENABLE = {17’b0_???};
wildcard bins LANE_DISABLE_PCLK_GATED = {17’b1_???0};
wildcard bins LANE_DISABLE_PCLK_ON = {17’b1_???1};
}

**
macros being used for sampling the covergroup**

define EVENT_pg_exit_cg (m_ctrl_vif.pipe_laneX_powerdown_skewed, m_chip_vif.phy_mplla_force_en, m_chip_vif.phy_mpllb_force_en, m_ctrl_vif.pipe_laneX_reset_n_skewed, m_ctrl_vif.pipe_rxX_disable, m_chip_vif.upcs_pipe_config, m_ctrl_vif.pipe_txX_disable, m_chip_vif.pg_mode_en, m_ctrl_vif.pipe_laneX_maxpclkreq, m_txrx_vif.pipe_txX_compliance, m_txrx_vif.pipe_txX_elecidle,m_ctrl_vif.pipe_laneX_rate_skewed, m_ctrl_vif.pg_reset) define SAMP_EVENT_pg_exit_cg 1,.sample1({m_ctrl_vif.pipe_laneX_powerdown_skewed,m_ctrl_vif.pipe_txX_disable,m_ctrl_vif.pipe_rxX_disable,m_chip_vif.upcs_pipe_config[9],m_chip_vif.upcs_pipe_config[6],m_ctrl_vif.pipe_laneX_reset_n_skewed,m_chip_vif.phy_mplla_force_en,m_chip_vif.phy_mpllb_force_en,m_ctrl_vif.pipe_laneX_rate_skewed,m_chip_vif.pg_mode_en,m_ctrl_vif.pg_reset,m_ctrl_vif.pipe_laneX_maxpclkreq}), .sample2({m_txrx_vif.pipe_txX_elecidle&m_txrx_vif.pipe_txX_compliance,m_chip_vif.upcs_pipe_config})

**
sampling of covergroup**

– This below forever loop is present inside the run_phase task of some monitor files And this m_lane_cg is the object of the file in which coverage is implemented.
forever begin
@(EVENT_pg_exit_cg) m_lane_cg.pg_exit_cg.sample(SAMP_EVENT_pg_exit_cg);
end

I hope this helps you to answer the query.

Regards
Abhinay

4

In reply to oasis_abhi:

That’s too much code to go through and still not enough to see what is happening. I suggest looking for help with a local peer to review your situation.

5

In reply to dave_59:
ok Dave, thanks for the help!

I’ll discuss it with a local peer.

-Abhinay