I cannot find any implementations of a class that extends uvm_reg_file
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1
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41
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March 23, 2025
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Access register/field value in DUT without acquiring the XatomicX semaphore
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0
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70
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September 25, 2024
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Uvm ral - explicit prediction
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2
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176
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May 27, 2024
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While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value
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2
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664
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January 10, 2024
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Access (to W/R) 2 Specific fields in a 32-bit register
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1
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314
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December 27, 2023
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Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test
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8
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1054
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November 21, 2023
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How ,to get type of instance_name
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4
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628
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July 11, 2023
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Variable type is not user defined type
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4
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1113
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May 27, 2023
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Getting Clock period Mismatch Error while comparing two clocks even though values of two clocks are same
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3
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652
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May 17, 2023
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RAL Model usage at SoC
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1
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622
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January 16, 2023
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NO_VIF: virtual interface must be set for:test.env.vif
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1
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993
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July 5, 2022
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Check the WO register for the value actually written
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2
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589
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June 14, 2022
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Report Catcher UVM
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1
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613
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May 15, 2022
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UVM RAL for configuration of TB in a SoC environment
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3
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1159
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February 23, 2022
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UVM RAL - multiple registers interfaces
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1
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898
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February 10, 2022
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Is there any scripts to generate the UVM_RAL using ralgen?
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1
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951
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January 10, 2022
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How to derive a register name from regmodel
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1
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1423
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October 20, 2021
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Read only regsiter access using RAL
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1
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1635
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June 29, 2021
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