Topics tagged Systemverilog-UVM-RAL

Topic	Replies	Views	Activity
Access register/field value in DUT without acquiring the XatomicX semaphore UVM UVM , Systemverilog-UVM-RAL	0	57	September 25, 2024
Uvm ral - explicit prediction UVM Systemverilog-UVM-RAL	2	136	May 27, 2024
While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value UVM UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model	2	548	January 10, 2024
Access (to W/R) 2 Specific fields in a 32-bit register UVM RAL , uvm-ral , Systemverilog-UVM-RAL	1	287	December 27, 2023
Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test UVM UVM , uvm_reg_hw_reset_seq , Mismatch-in-read-and-mirrored-value , Systemverilog-UVM-RAL , RAL-UVM , RAL-UVM-PREDICTOR	8	892	November 21, 2023
How ,to get type of instance_name SystemVerilog SystemVerilog , System-Verilog , Systemverilog-UVM-RAL	4	561	July 11, 2023
Variable type is not user defined type UVM UVM , mixed-UVM-OVM , User-defined-variable , Systemverilog-UVM-RAL , uvm-compilation	4	1006	May 27, 2023
Getting Clock period Mismatch Error while comparing two clocks even though values of two clocks are same UVM UVM , SV , Systemverilog-UVM-RAL , clockcheck , SV-UVM-clockcheck	3	649	May 17, 2023
RAL Model usage at SoC UVM UVM , Systemverilog-UVM-RAL , RAL-efficient , RAL-UVM-PREDICTOR	1	601	January 16, 2023
NO_VIF: virtual interface must be set for:test.env.vif UVM UVM , Systemverilog-UVM-RAL	1	949	July 5, 2022
Check the WO register for the value actually written UVM UVM , Systemverilog-UVM-RAL , RAL-UVM	2	583	June 14, 2022
Report Catcher UVM UVM UVM , report-catcher , Systemverilog-UVM-RAL	1	607	May 15, 2022
UVM RAL for configuration of TB in a SoC environment UVM UVM , Systemverilog-UVM-RAL	3	1143	February 23, 2022
UVM RAL - multiple registers interfaces UVM UVM , Systemverilog-UVM-RAL	1	884	February 10, 2022
Is there any scripts to generate the UVM_RAL using ralgen? UVM UVM , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , RAL-efficient	1	908	January 10, 2022
How to derive a register name from regmodel UVM SystemVerilog , UVM , get_registers-method-for-uvm_reg_block , Systemverilog-UVM-RAL , regmodel , get_reg_by_name	1	1359	October 20, 2021
Read only regsiter access using RAL UVM UVM , Systemverilog-UVM-RAL	1	1505	June 29, 2021