I want to check type of instance_name on systemVerilog, by implementing boucle "if else ". How to do it ?
Thanks
In reply to uvm_share:
Assume there is a check_type(instance_name) function. What are you expecting it to do? And how would you use it? Try explaining with example code.
Therer is my code i want to check type of instance (master_interface), so for making this, what is the right way to follow ?
ahb_interface master_interface ;
if (master_interface instanceof ahb_interface) begin
$display ("Ok") ;
end
else
$display ("NO");
In reply to uvm_share:
That really does not explain what you are trying to accomplish. ahb_interface appears on the line above the if statement. How could you not know it is an ahb_interface?
In reply to uvm_share:
Not a suggestion, but you can accomplish this with $typename. Here’s an example:
module dut;
class myclass;
endclass
initial begin
myclass myclass_inst = new();
string myclass_inst_str = $typename(myclass_inst);
string myclass_str = $typename(myclass);
$display("type_str: %s inst_str: %s", myclass_str, myclass_inst_str);
if (myclass_str == myclass_inst_str) begin
$display("SUCCESS");
end else begin
$display("FAILURE");
end
end
endmodule