Topics tagged RAL-UVM

Topic	Replies	Views	Activity
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	5	41	April 23, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	976	April 16, 2024
Uvm_mem reference codes UVM RAL-UVM	2	80	April 4, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	86	February 26, 2024
While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value UVM UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model	2	253	January 10, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	127	December 29, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	193	December 6, 2023
Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test UVM UVM , uvm_reg_hw_reset_seq , Mismatch-in-read-and-mirrored-value , Systemverilog-UVM-RAL , RAL-UVM , RAL-UVM-PREDICTOR	8	484	November 21, 2023
Multiple Reset for RAL UVM UVM , RAL-UVM , multiple-reset	2	222	November 7, 2023
APB2SPI Clock Period Checking Assertion Placement UVM UVM , assertion , SPI , clock-frequency , APB , RAL-UVM	0	165	August 10, 2023
Ral Model with multiple instance of same reg block with restriction on port accessing UVM UVM , RAL-UVM	1	209	July 8, 2023
Bit Bashing special Register UVM UVM , RAL-UVM	1	231	June 12, 2023
System verilog compiler directive Q SystemVerilog SystemVerilog , System-Verilog , Verilog , RAL-UVM , compiler	0	330	May 13, 2023
[Register Models]: Is there a way to automate the generation of backdoor paths for registers? UVM UVM , RAL-UVM	1	319	February 24, 2023
A race condition between threads concurrently accessing the register model UVM UVM , RAL-UVM	1	384	September 8, 2022
RAL model byte_en UVM UVM , RAL-UVM	2	670	July 4, 2022
Check the WO register for the value actually written UVM UVM , Systemverilog-UVM-RAL , RAL-UVM	2	419	June 14, 2022
UVM/REG/DUPLROOT issue in UVM RAL UVM UVM , RAL-UVM	0	364	May 17, 2022
Send_request failed to cast sequence item. User type = uvm_reg_item UVM UVM , sequence-item , RAL-UVM	1	383	May 5, 2022
Backdoor write is not working, if questa tool problem what is the commands need for backdoor to work? UVM UVM , Backdoor_access-HDL-access-methods , backdoor-read_wrie , RAL-UVM	1	596	March 23, 2022
Read and Write for a memory in UVM_RAL UVM UVM , RAL-UVM	1	615	March 23, 2022
RAL read and write issues to Design UVM UVM , RAL , RAL-UVM	9	1183	March 7, 2022
FATAL error in config_db while trying to get object in sequence UVM UVM , systemverilog-uvm , RAL-UVM	1	711	February 28, 2022
Functions inside apb adapter are not being called from the test sequence UVM UVM , RAL , RAL-UVM , uvmral	2	633	February 23, 2022
TYCMPAT error for UVM config db get method UVM UVM , uvm-config_db , RAL-UVM	1	603	February 14, 2022
How to access fields in encrypted UVM reg model UVM UVM , uvm_reg , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	2	514	February 11, 2022
Is there any scripts to generate the UVM_RAL using ralgen? UVM UVM , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , RAL-efficient	1	745	January 10, 2022
Different RESET Type on UVM register model UVM UVM , RAL-UVM	3	1571	January 10, 2022
UVM RAL and volatile fields X prediction UVM UVM , RAL-UVM	3	1364	October 12, 2021