Topics tagged RAL-UVM

Topic	Replies	Views	Activity
Uvm reg block override using factory override UVM RAL-UVM	9	102	September 12, 2025
Reg_block.get_reg_by_name returns unexpected null UVM RAL , uvm-ral , RAL-UVM	0	32	July 30, 2025
First Step in Design Verification UVM UVM , Verification , Formal-Verification , RAL-UVM	2	153	May 27, 2025
I cannot find any implementations of a class that extends uvm_reg_file UVM SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure	1	59	March 23, 2025
UVM RAL, APB WRITE seen but sequence struck UVM RAL-UVM	4	74	March 3, 2025
Query on uvm_reg_hw_reset_seq UVM RAL-UVM	1	114	August 19, 2024
Different RESET Type on UVM register model UVM UVM , RAL-UVM	5	2103	July 3, 2024
Skipping a register field from comparison with RAL UVM RAL , uvm_ral , RAL-UVM	10	744	May 15, 2024
[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique UVM SystemVerilog , UVM , uvm_reg , RAL-UVM	1	1349	April 16, 2024
Uvm_mem reference codes UVM RAL-UVM	2	309	April 4, 2024
Question related to RAL methods SystemVerilog UVM , RAL , uvm_ral , RAL-UVM	0	308	February 26, 2024
While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value UVM UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model	2	783	January 10, 2024
In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor? UVM UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM	0	314	December 29, 2023
I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers UVM UVM , RAL , RAL-UVM	0	321	December 6, 2023
Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test UVM UVM , uvm_reg_hw_reset_seq , Mismatch-in-read-and-mirrored-value , Systemverilog-UVM-RAL , RAL-UVM , RAL-UVM-PREDICTOR	8	1173	November 21, 2023
Multiple Reset for RAL UVM UVM , RAL-UVM , multiple-reset	2	521	November 7, 2023
APB2SPI Clock Period Checking Assertion Placement UVM UVM , assertion , SPI , clock-frequency , APB , RAL-UVM	0	368	August 10, 2023
Ral Model with multiple instance of same reg block with restriction on port accessing UVM UVM , RAL-UVM	1	334	July 8, 2023
Bit Bashing special Register UVM UVM , RAL-UVM	1	404	June 12, 2023
System verilog compiler directive Q SystemVerilog SystemVerilog , System-Verilog , Verilog , RAL-UVM , compiler	0	448	May 13, 2023
[Register Models]: Is there a way to automate the generation of backdoor paths for registers? UVM UVM , RAL-UVM	1	401	February 24, 2023
A race condition between threads concurrently accessing the register model UVM UVM , RAL-UVM	1	633	September 8, 2022
RAL model byte_en UVM UVM , RAL-UVM	2	995	July 4, 2022
Check the WO register for the value actually written UVM UVM , Systemverilog-UVM-RAL , RAL-UVM	2	596	June 14, 2022
UVM/REG/DUPLROOT issue in UVM RAL UVM UVM , RAL-UVM	0	571	May 17, 2022
Send_request failed to cast sequence item. User type = uvm_reg_item UVM UVM , sequence-item , RAL-UVM	1	542	May 5, 2022
Backdoor write is not working, if questa tool problem what is the commands need for backdoor to work? UVM UVM , Backdoor_access-HDL-access-methods , backdoor-read_wrie , RAL-UVM	1	762	March 23, 2022
Read and Write for a memory in UVM_RAL UVM UVM , RAL-UVM	1	787	March 23, 2022
RAL read and write issues to Design UVM UVM , RAL , RAL-UVM	9	1527	March 7, 2022
FATAL error in config_db while trying to get object in sequence UVM UVM , systemverilog-uvm , RAL-UVM	1	1064	February 28, 2022

Uvm reg block override using factory override

UVM

RAL-UVM

9

102

September 12, 2025

Reg_block.get_reg_by_name returns unexpected null

UVM

RAL , uvm-ral , RAL-UVM

0

32

July 30, 2025

First Step in Design Verification

UVM

UVM , Verification , Formal-Verification , RAL-UVM

2

153

May 27, 2025

I cannot find any implementations of a class that extends uvm_reg_file

UVM

SystemVerilog , UVM , RAL , System-Verilog , uvm-ral , uvm_ral , uvm_reg_file , UVM-RAL-systemverilog-ralmodelling , Systemverilog-UVM-RAL , RAL-UVM , register-file , register-model-structure

1

59

March 23, 2025

UVM RAL, APB WRITE seen but sequence struck

UVM

RAL-UVM

4

74

March 3, 2025

Query on uvm_reg_hw_reset_seq

UVM

RAL-UVM

1

114

August 19, 2024

Different RESET Type on UVM register model

UVM

UVM , RAL-UVM

5

2103

July 3, 2024

Skipping a register field from comparison with RAL

UVM

RAL , uvm_ral , RAL-UVM

10

744

May 15, 2024

[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique

UVM

SystemVerilog , UVM , uvm_reg , RAL-UVM

1

1349

April 16, 2024

Uvm_mem reference codes

UVM

RAL-UVM

2

309

April 4, 2024

Question related to RAL methods

SystemVerilog

UVM , RAL , uvm_ral , RAL-UVM

0

308

February 26, 2024

While doing uvm_reg_hw_reset_seq getting error stating value read from DUT does not match mirrored value

UVM

UVM , Systemverilog-UVM-RAL , RAL-UVM , model-uvm-reference_model

2

783

January 10, 2024

In UVM RAL, I have 2 active agentS,only one adaptor. how to work 2 transaction in one adaptor?

UVM

UVM , RAL , RAL-register-UVM , uvm-ral , UVM-RAL-systemverilog-ralmodelling , RAL-UVM

0

314

December 29, 2023

I had an issue regarding RAL, i am unable to create a map which should contains maps of different invidual registers

UVM

UVM , RAL , RAL-UVM

0

321

December 6, 2023

Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

UVM

UVM , uvm_reg_hw_reset_seq , Mismatch-in-read-and-mirrored-value , Systemverilog-UVM-RAL , RAL-UVM , RAL-UVM-PREDICTOR

8

1173

November 21, 2023

Multiple Reset for RAL

UVM

UVM , RAL-UVM , multiple-reset

2

521

November 7, 2023

APB2SPI Clock Period Checking Assertion Placement

UVM

UVM , assertion , SPI , clock-frequency , APB , RAL-UVM

0

368

August 10, 2023

Ral Model with multiple instance of same reg block with restriction on port accessing

UVM

UVM , RAL-UVM

1

334

July 8, 2023

Bit Bashing special Register

UVM

UVM , RAL-UVM

1

404

June 12, 2023

System verilog compiler directive Q

SystemVerilog

SystemVerilog , System-Verilog , Verilog , RAL-UVM , compiler

0

448

May 13, 2023

[Register Models]: Is there a way to automate the generation of backdoor paths for registers?

UVM

UVM , RAL-UVM

1

401

February 24, 2023

A race condition between threads concurrently accessing the register model

UVM

UVM , RAL-UVM

1

633

September 8, 2022

RAL model byte_en

UVM

UVM , RAL-UVM

2

995

July 4, 2022

Check the WO register for the value actually written

UVM

UVM , Systemverilog-UVM-RAL , RAL-UVM

2

596

June 14, 2022

UVM/REG/DUPLROOT issue in UVM RAL

UVM

UVM , RAL-UVM

0

571

May 17, 2022

Send_request failed to cast sequence item. User type = uvm_reg_item

UVM

UVM , sequence-item , RAL-UVM

1

542

May 5, 2022

Backdoor write is not working, if questa tool problem what is the commands need for backdoor to work?

UVM

UVM , Backdoor_access-HDL-access-methods , backdoor-read_wrie , RAL-UVM

1

762

March 23, 2022

Read and Write for a memory in UVM_RAL

UVM

UVM , RAL-UVM

1

787

March 23, 2022

RAL read and write issues to Design

UVM

UVM , RAL , RAL-UVM

9

1527

March 7, 2022

FATAL error in config_db while trying to get object in sequence

UVM

UVM , systemverilog-uvm , RAL-UVM

1

1064

February 28, 2022