Uvm_mem reference codes

I have a doubt about memory IP verification with UVM RAL Backdoor.

We verified all the IP feature related tests in UVM and also verified wr/rd into memory using the RAL frontdoor mechanism. We have a doubt on verifying it using RAL backdoor mechanism.

Approach-1: We have mimicked complete memory logic in our write monitor(expected data) and through dut hdl_path, we accessed DUT locations and stored the data(actual data) and then compared the expected data versus actual data in the scoreboard.

Approach-2 : Instead of this approach-1, can we do the memory verification with UVM_MEM present in the RAL model? If so, could you please provide us with any examples for it.

We don’t have any reference codes to explore.
Could you please help us with this.

Thank you.

Maybe this can point you in the right direction w.r.t Approach 2 basically it defines a uvm_mem to be used for verification of the functionality expected in the design along with some handy custom backdoor path definition, also the paper that is referred in the example is a good pointer.


Thank you rgarcia07. I’ll go through it.