UVM RAL, APB WRITE seen but sequence struck

HI All,

I have written APB UVC for doing register writes/reads & I have written register adapter. Write is initiated from a sequence and after that I can see write transaction in waveform (register value is also updated), I see print statements from register adapter & predictor model on transaction. After that next statements in sequence were not executing, not sure what is happening after that.

here is the waveform (write transaction)

print statements from adapter & predictor

UVM_INFO /sw/cadence/xcelium/24.09.005HF/tools/methodology/UVM/CDNS-1.2/sv/src/reg/uvm_reg_predictor.svh(221) @ 16000.000ps: uvm_test_top.pc_env.reg_predictor [REG_PREDICT] Observed WRITE transaction to register regmodel.dbg_buf_ctrl: value='h1 : updated value = 'h1

please let me know if I am missing anything.

Without seeing any code, it is difficult to provide any suggestions.

Can you share the code on EDA Playground?

I have taken screenshot of the code, would this be fine ?

reg adapter model:

apb sequence:
image

apb driver:


image

apb monitor:

apb intf:
image

env:
build phase

connect phase

sequence where write is initiated:

Print statements:

from adapter

from predictor
UVM_INFO /sw/cadence/xcelium/24.09.005HF/tools/methodology/UVM/CDNS-1.2/sv/src/reg/uvm_reg_predictor.svh(221) @ 16000.000ps: uvm_test_top.pc_env.reg_predictor [REG_PREDICT] Observed WRITE transaction to register regmodel.dbg_buf_ctrl: value='h1 : updated value = 'h1

waveform:

Without being able to run the code and reproduce the issue, it is difficult to provide any suggestions.

Can you share the code on EDA Playground?

HI cgales,

I will try to create a dummy DUT(in the above run, DUT is my companies RTL) and I will share the code in EDA in some time.

Thanks.

Regards,
Sudarshan