Topic	Replies	Views	Activity
How to verify this master slave interface UVM Verification	0	74	August 5, 2025
First Step in Design Verification UVM UVM , Verification , Formal-Verification , RAL-UVM	2	213	May 27, 2025
Do we need to verify reserved bits/registers in the verification procedure? UVM Verification	4	107	May 12, 2025
How to improve as a verification engineer? UVM UVM , System-Verilog , Verification , experience	0	547	April 16, 2023
FREE with promotion: Real Chip Design and Verification Using Verilog and VHDL Announcements Announcements , Verification , chip-design	0	1188	July 13, 2020
OOPs based testbench of combinational adder SystemVerilog SystemVerilog , OOPS , Verification , layered-testbench	3	1468	August 23, 2019
Does backdoor register access violate true black box verification principles? SystemVerilog SystemVerilog , Verification , UVM-RAL-Backdoor-Write-hdl_path	1	1204	January 10, 2018
New book: SystemVerilog Assertions Handbook, 4th Edition SystemVerilog SystemVerilog , assertion , Verification , testbenching	4	10707	September 19, 2016
Difference Between SoC Verification and VIP/IP Verification? UVM UVM , SOC , Verification , VIP	1	15034	September 9, 2016
Verification of dut.how to acess UVM UVM , DUT , Verification	5	1638	June 29, 2016
Problem with DUT DDR input -> SDR output OVM OVM , Verification , modelsim , Xilinx , unisim , ddr	1	2447	March 11, 2016
Separate code of generator and driver SystemVerilog SystemVerilog , Verification	3	1826	March 25, 2015
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	13533	September 23, 2014
UVM vs SystemVerilog UVM SystemVerilog , UVM , Verification , Advantages	2	3806	July 17, 2014

Verification