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How to verify this master slave interface
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0
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74
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August 5, 2025
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First Step in Design Verification
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2
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213
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May 27, 2025
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Do we need to verify reserved bits/registers in the verification procedure?
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4
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107
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May 12, 2025
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How to improve as a verification engineer?
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0
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547
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April 16, 2023
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FREE with promotion: Real Chip Design and Verification Using Verilog and VHDL
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0
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1188
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July 13, 2020
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OOPs based testbench of combinational adder
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3
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1468
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August 23, 2019
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Does backdoor register access violate true black box verification principles?
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1
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1204
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January 10, 2018
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New book: SystemVerilog Assertions Handbook, 4th Edition
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4
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10707
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September 19, 2016
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Difference Between SoC Verification and VIP/IP Verification?
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1
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15034
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September 9, 2016
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Verification of dut.how to acess
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5
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1638
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June 29, 2016
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Problem with DUT DDR input -> SDR output
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1
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2447
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March 11, 2016
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Separate code of generator and driver
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3
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1826
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March 25, 2015
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Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification
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11
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13533
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September 23, 2014
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UVM vs SystemVerilog
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2
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3806
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July 17, 2014
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