Hi Guys,
Can someone help me educate on the topic : comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification
Please help
If you are asking specifically about verification, and not design, then we will suggest that you make the comparison with SystemVerilog versus VHDL or Verilog. Developing a verification test is a software programming task, not a design task. SystemVerilog was developed to merge the two worlds together in a single language, plus added features specifically for functional coverage and constrained random test generation. The UVM base class library and methodology is the established standard for writing verification testbenches, and that gives you access to a plethora of standard methodology guidelines, training, and Verification IP.
In reply to dave_59:
so is it likee using Verilog or VHDL doesnt matter much when it comes to verification ?
In reply to jvkodali:
If you are asking whether it matters whether you use Verilog or VHDL for RTL design when you are using SystemVerilog/UVM for verification, I would say use the language that you have the resources to support. IMHO, it think it would be better if everyone used SystemVerilog for both design and verification. That way it is easier to shift resources between design and verification. However, there are some people that believe it is best for verification if verification engineers did not understand how to read RTL code. I don’t agree with that.
In reply to dave_59:
I completely get your point and I support it to the core.
But here my context is to just know the comparision so that I get a better understanding of the subject ( as i am a begginer ) and present the comparision.
I have been googling but haven’t been successful yet. I would appreciate if you could help me get the main reasons what are adv or disadv of using Verilog or VHDL in Verification domain only (Not DESIGN)
Thank you
In reply to jvkodali:
If you are only talking about the verification domain, then the comparison needs to be between VHDL and SystemVerilog, not Verilog. SystemVerilog has all the dynamic software programming features that you need to create a testbench, and the object-oriented programming features to make that testbench reusable. And then there are are the testbench specific features that I mentioned at the beginning of my response. But you can’t just look at the technical features. There is the cost of getting people trained, especially if you have only VHDL expertise in-house. And then you have to look at the available verification IP that you may need in case you do not have the resources available to write it yourself (How much time to you want to spend verifying your testbench instead of your DUT?). That’s where SystemVerilog along with standard UVM based verification IP can help you tremendously.
In reply to jvkodali:
I was asked to prepare a presentation on the topic below for a job interview:
Comparision of Advantages/Disadvantges of Verilog or VHDL in Hardware verification
That’s a good interview question because it demonstrates how much you really know about design and verification. It is also a tricky question because it can also show the weaknesses in your understanding of the whole verification problems. Thus, you need to address the process of verification, including:
- requirements: How defined
- verification plan: What’s in it, what to test
- verification architecture and methodologies
- Use of assertions
- Use of constrained-random tests
- Use of coverage (functional being of importance here)
- Maybe formal verification?
- Use of UVM (maybe)
- Languages
- Limits of VHDL for verification
- Features of SystemVerilog supporting verification
I authored several books on VHDL and Verilog (which represents the RTL part of SystemVerilog) and to me, the two languages are pretty much similar, except for syntax. After being a very strong advocate of VHDL, I changed my beliefs and switched to SystemVerilog, even for just the Verilog subset of it. It is less restrictive, but requires good coding guidelines. I am also a very strong advocate of SystemVerilog assertions (SVA) because they help in the clarification of the requirements and in the debugging and verification process. Formal verification is gaining wide acceptance, and uses SVA for the definitions of the properties of the design. I also like the UVM methodology and approaches, though UVM is not very straightforward, and requires care, with a good understanding of SystemVerilog. However, with some guidance and rules, I believe that one can effectively use UVM with a lesser than full
understanding of SystemVerilog. What I am talking about it is the use of predefined templates for the basic building blocks.
Best wishes in your endeavors, and show a good understanding of the whole verification issues; the languages are just vehicles to achieve those goals, and though important, they are not the whole solution.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
In reply to ben@SystemVerilog.us:
Hi Ben,
Thanks for your insight. I understand that a lot depends on the Verification methodology.
Are there any language specific features that help in Verification. I would appreciate any information contrasting Verilog, VHDL and System Verilog for Verification.
Because of various opinions and no clear resourses on Web on this particualar topic, I am finding it difficult. All comparisions are in general talking about the general features.
I came accross one of your thread from 2000.
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=66
I look forward to hearing from you soon.
In reply to jvkodali:
Are there any language specific features that help in Verification.
SV supports specific features for verifcation, and those are not supported by VHDL.
Several aspects are needed in verif:
- Stimulus generator. For that SV supports:
a) Constraint random generation with random gen stability.
FYI, on rnd stability: This explains it: WWW.TESTBENCH.IN - Systemverilog Randomization
Basically, this deals with reproducability because of calls to RNG (random number generator_.
in Verilog, there is 1 RNG with the $random(), thus if you make changes to modules (or threads) that call the RNG (e.g., module x adds one more RNG in this new model) you would not get the same random numbers as the previous run.
In SystemVerilog seeding will be done hierachily. Every module instance, interface instance, program instance and package has initialization RNG. Every thread and object has independent RNG . When ever dynamic thread is created its RNG is initialized with the next random value from its parent thread. RNG initialization and RNG generation are different process (see the link for more info). But that works with the $urandom,$urandom_range, or std::randomize()
Thus, in a nutshell, the $random is verilog thingy, whereas $urandom,$urandom_range, or std::randomize() are SV where each thread has its own RNG; if one thread adds another RNG call, it does not disturb the other RNGs in the other threads.
-
Verification of results:
This is supported by SVA and by dta structures needed for verif. Am thinking of stuff like associative arrays, queus, mailboxes, the generate statement (like VHDL), vectors. -
Coverage to determine when done, or how much was done.
SV has the cSVA cover and the covergroup to help in that respect. -
flexibility for changes
SV has classes that can be extended and dynamically linked to other classes to accommodate changes and tests. -
standards: UVM was developed to facilitate the standardization for the development of TBs.
On Verilog, as Dave mentioned, it is a subset of SV, and more at the RTL level. Not very useful for the verif of large designs.
On VHDL, it lacks the above aspects.
Ben Cohen systemverilog.us
In reply to ben@SystemVerilog.us:
But using VHDL or Verilog will help designers verify in the eariler stages of design right.
What are the features in VHDl that makes it good.
In reply to jvkodali:
But using VHDL or Verilog will help designers verify in the earlier stages of design right.
- When you say “Verilog”, you mean you want to constrain yourself to that subset of SystemVerilog that was nitiall designed for RTL with some basic verification features.
- Thus, unless you have an antique simulator, when you run Verilog, you are running SystemVerilog.
- For a quick and dirty testbench to test the “earlier stages of design”, SystemVerilog offers very nice features. Below are links to very quick and dirty testbench applications of SystemVerilog for quick design tests (notice how short and efficient they are).
http://systemverilog.us/simple_testbench.png
http://systemverilog.us/counter_max_tb_simple.sv http://systemverilog.us/counter_pkg.sv
For VHDL, you would need to add a randomize package (have not use VHDL for many, many years, so I cant give a link or more info, but you need a package). The randomize package is not “stable”, as explained in my previous reply. Also, you would need to create some code to define or emulate constraints. Of course, in both languages, you can define directed tests … have fun!!!
What are the features in VHDl that makes it good.
The problem with VHDL is that it was not updated with features necessary for verification. Some work was (and is being done) to add packages, but IMHO, the effort is not very strongly supported. I find SystemVerilog very useful for design and verification, even for the quick and dirty models just to check the sanity of small design partitions, as demoed in the above links. I’ll let someone else tell you how great VHDL is (FWIW, I authored 8 books that cover VHDL).
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115