Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification

SystemVerilog
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In reply to dave_59:

I completely get your point and I support it to the core.

But here my context is to just know the comparision so that I get a better understanding of the subject ( as i am a begginer ) and present the comparision.

I have been googling but haven’t been successful yet. I would appreciate if you could help me get the main reasons what are adv or disadv of using Verilog or VHDL in Verification domain only (Not DESIGN)

Thank you