Topics tagged functional-verification

Topic	Replies	Views	Activity
SystemVerilog assertions in synthesized design SystemVerilog SystemVerilog , functional-verification , SVA-Assertion , post-synthesis-verification	4	4663	January 8, 2021
Same sequence on multiple sequencers UVM SystemVerilog , UVM , functional-verification , uvm-verilog	1	1068	September 19, 2018
Comparison of the advantages/disadvantages of using VHDL or Verilog for hardware verification SystemVerilog SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog	11	13393	September 23, 2014
What is the standard methodology of verifying HW when there are cases where RTL and Goldenmodel might produce different but correct output? UVM UVM , scoreboard , Constraint-random-verification , functional-verification , checker	1	1571	May 22, 2014
Check out this new free and on line course on System Verilog basics and provide feedback Announcements Announcements , System-Verilog , functional-verification , online-course , SOC-verification	0	5429	April 24, 2014

SystemVerilog assertions in synthesized design

SystemVerilog , functional-verification , SVA-Assertion , post-synthesis-verification

4

4663

January 8, 2021

Same sequence on multiple sequencers

SystemVerilog , UVM , functional-verification , uvm-verilog

1

1068

September 19, 2018

SystemVerilog , testbench-environment , functional-verification , VHDL , Verification , Verilog

11

13393

September 23, 2014

UVM , scoreboard , Constraint-random-verification , functional-verification , checker

1

1571

May 22, 2014

Announcements , System-Verilog , functional-verification , online-course , SOC-verification

0

5429

April 24, 2014