Topics tagged SOC-verification

Topic	Replies	Views	Activity
How do we reuse a constraint in IP level at SOC level? SystemVerilog SOC-verification	0	111	October 27, 2024
What are the various approaches for verifying a design that contain an ARM processor like A9,A72,R5 etc in UVM? UVM SOC-verification , processor-verification , FPGA-Verification , Top-level-verification , Chip-level-verification , ASIC-Verification	0	176	July 24, 2024
SOC Verification - Write C test where 32 bit processor will write the 64 bit memory (each location=64 bit/ Depth=65 ) SystemVerilog SystemVerilog , SOC-verification , c-tests	2	500	January 1, 2024
Running C code on ARM based CPU in SoC, looking for handshake mechanism between C and SystemVerilog code SystemVerilog SystemVerilog , SOC-verification , CPU , ARM	2	2825	October 15, 2020
Guidelines to takecare when integrating UVM Env for Module to SoC Level UVM UVM , configuration , SOC-verification , coding-guidelines , reusable	1	1278	August 14, 2018
Cross coverage between two covergroups SystemVerilog SystemVerilog , cross-coverage , SOC-verification , covergroup	3	2069	October 2, 2017
Test feature verification UVM UVM , SOC-verification	5	2203	May 30, 2017
Web Seminar Notification: Breaking the Speed Limits on SoC Verification with the Questa® Flow Announcements Announcements , SOC-verification , Web-Seminar , Questa-Simulator	0	2091	May 15, 2017
How to reuse the bfm tasks written at DUT level during SOC integration? UVM UVM , SOC-verification , VIP-integration , UVM-reuse	1	1428	November 14, 2016
Intigrating VIP in SOC environment UVM UVM , SOC-verification , UVM-system-verilog , SOC , VIP-integration	1	4104	September 4, 2014
Check out this new free and on line course on System Verilog basics and provide feedback Announcements Announcements , System-Verilog , functional-verification , online-course , SOC-verification	0	5442	April 24, 2014