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How do we reuse a constraint in IP level at SOC level?
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0
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111
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October 27, 2024
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What are the various approaches for verifying a design that contain an ARM processor like A9,A72,R5 etc in UVM?
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0
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176
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July 24, 2024
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SOC Verification - Write C test where 32 bit processor will write the 64 bit memory (each location=64 bit/ Depth=65 )
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2
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500
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January 1, 2024
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Running C code on ARM based CPU in SoC, looking for handshake mechanism between C and SystemVerilog code
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2
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2825
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October 15, 2020
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Guidelines to takecare when integrating UVM Env for Module to SoC Level
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1
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1278
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August 14, 2018
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Cross coverage between two covergroups
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3
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2069
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October 2, 2017
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Test feature verification
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5
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2203
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May 30, 2017
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Web Seminar Notification: Breaking the Speed Limits on SoC Verification with the Questa® Flow
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0
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2091
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May 15, 2017
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How to reuse the bfm tasks written at DUT level during SOC integration?
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1
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1428
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November 14, 2016
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Intigrating VIP in SOC environment
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1
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4104
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September 4, 2014
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Check out this new free and on line course on System Verilog basics and provide feedback
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0
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5442
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April 24, 2014
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