Topics tagged CPU

Topic	Replies	Views	Activity
Is there a way to make the force value propagate beyond the double assigned wire SystemVerilog SystemVerilog , Verilog , signal_force , FORCE , CPU	1	256	September 12, 2023
UVM Report Summary is being printed twice in a test log UVM UVM , SOC , uvm-objection , CPU , UVM_Report_Summary	1	827	November 22, 2020
Running C code on ARM based CPU in SoC, looking for handshake mechanism between C and SystemVerilog code SystemVerilog SystemVerilog , SOC-verification , CPU , ARM	2	2680	October 15, 2020