UVM Report Summary is being printed twice in a test log

UVM
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1

Hi,

I have an ARM CPU running a C-code loaded into it’s memory.
In the main_phase of the SV test, I have the next code:


    task main_phase (uvm_phase phase);
        super.main_phase(phase);
        `uvm_info(get_full_name(), $sformatf("Raising main phase objection"), UVM_NONE)
        phase.raise_objection(this);
        `uvm_info("ENV_PHASE", $sformatf("main_phase started"), UVM_NONE)
        `uvm_info(get_full_name(), $sformatf("Dropping main phase objection"), UVM_NONE)
        phase.drop_objection(this);
    endtask

After the objection is dropped in this main_phase, the “UVM Report Summary” is being printed.
But test keeps running and report continues to issue prints, till C-code loaded into the CPU is finished.
And then the “UVM Report Summary” is being printed again.

Any idea/clues why a “UVM Report Summary” can be printed more than once in the test report?
Issue with objections?

Thanks!

2

In reply to Michael54:
You are showing only very liitel of your code. Using objections in your test is useless, because you are not doing anything here. It raises and drops immediately.
Remove the objections here it might answer your question.