Is there a way to make the force value propagate beyond the double assigned wire

SystemVerilog
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1

I want to connect testbench to CPU bus in an intermittent manner. The simulation starts with CPU handling traffic, and then verification takes over.
I tried the following code, but the result is X.


`timescale 1ns/1ns
module test_force;
   wire tb;
   wire cpu;
   wire dut;

   assign cpu = 1;
   assign dut = cpu;
   assign dut = tb;

   initial begin
     #2 force tb = 0;
     #200 $finish;
   end
endmodule
2

In reply to akivama:

Multiple assign statements to a wire will cause issues.

Perhaps you want to use a mux to select which input to use?


bit use_tb = 0;
assign dut = use_tb ? tb : cpu;

You can change the value of use_tb to select either tb or cpu to drive dut.