Announcements

Topic	Replies	Views	Activity
Please format your code with markdown or <code> </code> tags Announcements See Formatting in Posts Your source code will be much easier to read when it is formatted nice and pretty like this: class packet; rand bit [31:0] address; rand bit [7:0] length; rand bit [7:0] data[]; con…	9	25063	August 8, 2024
About the Announcements category	0	181	January 1, 2023
Welcome to our Verification Academy community!	1	397	September 13, 2023
Web Seminar - Beyond UVM: Effectively Modeling and Analyzing Coverage Announcements , Web-Seminar , Verification-Cookbook	0	3598	November 21, 2012
UVM/OVM Recipe of the Month - Intro to UVM Registers Announcements	0	5743	October 4, 2011
Have you heard? There's a new Academy course, Introduction to the UVM Announcements , UVM , Course , Ray-Salemi	0	1858	August 6, 2014
Web Seminar Notification: New School Thinking for Fast and Efficient Verification Using EZ-VIP Announcements , Verification-Academy-Technology-Series , Verification-IP	0	1657	April 20, 2015
Web Seminar Notification: New School Coverage Closure Announcements , Verification-Academy-Technology-Series , Questa-CoverCheck	0	1614	May 20, 2015
New Forums interface - URL changed, subtle fix	0	158	December 24, 2023
Designing and Verifying a processor Announcements , processor , project , self-learning	1	429	October 16, 2023
Arm Assembly Language Community Announcements , ARM , AssemblyLanguage , ArmV8	1	310	September 8, 2023
Changing employer email address associated with the account Announcements	1	447	January 20, 2023
SVA - set the number of failures Announcements , limit-SVA	1	476	November 6, 2022
GUI Based UVM Testbench Template Generator Announcements	1	2745	June 7, 2022
VMM, Free book: A Pragmatic Approach to VMM Adoption Announcements	0	619	May 24, 2022
New to Verification Academy Announcements , beginner , uvm_beginner	0	394	May 19, 2022
Simple and very powerful free SystemVerilog editor Announcements	3	9108	April 23, 2021
Anecdote: Is SVA a soap pipe? Announcements	0	664	February 18, 2021
Verification Horizons Blog - Stay Updated Announcements , Verification-Horizons	0	1441	August 13, 2020
Verification Horizons - July 2020 Issue Announcements , Verification-Horizons	0	805	July 17, 2020
FREE with promotion: Real Chip Design and Verification Using Verilog and VHDL Announcements , Verification , chip-design	0	1094	July 13, 2020
Change email address of Verification Academy and EDA Playground full accounts? Announcements , email-address , account , content	1	1483	June 9, 2020
Functional Verification Web Seminars: 5-Part Weekly Series Announcements , Formal-Verification , Web-Seminar , Verification-IP , Questa-Simulation , CDCRDC	0	888	May 11, 2020
On Demand Web Seminar Recording: UVM Coding Guidelines: Tips & Tricks You Probably Didn’t Know SystemVerilog , Announcements , UVM , Web-Seminar , Chris-Spear	0	1160	April 10, 2020
Verification Horizons - March 2020 Issue Announcements , Verification-Horizons	0	938	March 3, 2020
Axi boundary calculation Announcements , AHB-burst , signal-width-calculation-assertions , axi-amba-protocol , AMBA-AXI , AXI-VIP	2	9285	February 19, 2020
Verification Horizons - December 2019 Issue Announcements , Verification-Horizons	0	1090	December 12, 2019
Seminar Notification: Portable Stimulus - Fremont, CA Announcements , Seminar , Questa-inFact , Portable-Stimulus , PSS	0	1036	September 23, 2019
Seminar Notification: Verification IP - Fremont, CA Announcements , Seminar , Verification-IP , Protocol-Standards , PCIe-Gen-5 , DDR-5	0	1031	September 16, 2019
UVM Framework Course - Two New Sessions Now Available Announcements , Course , UVM-Framework , UVMF , Bob-Oden	0	1155	September 10, 2019

Please format your code with markdown or <code> </code> tags

Announcements

See Formatting in Posts Your source code will be much easier to read when it is formatted nice and pretty like this: class packet; rand bit [31:0] address; rand bit [7:0] length; rand bit [7:0] data[]; con…