Topics tagged AMBA-AXI

Topic	Replies	Views	Activity
Axi boundary calculation Announcements Announcements , AHB-burst , signal-width-calculation-assertions , axi-amba-protocol , AMBA-AXI , AXI-VIP	3	9710	June 5, 2025
AXI UVM question/advice UVM UVM , AMBA-AXI	0	223	January 30, 2025
Data width is 128 bits but only LSB 32-bits are valid UVM UVM , AMBA-AXI	11	2352	October 2, 2024
AXI narrow transfer SystemVerilog OVM , axi-driver , axi , axi-amba-protocol , AMBA-AXI , AXI-VIP , AXI4-Stream	0	473	August 27, 2024
I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave UVM SystemVerilog , UVM , AMBA-AXI , AMBA-VIP , model-uvm-reference_model , coverage-UVM-module-class	3	830	August 24, 2023
AXI based Q UVM UVM , System-Verilog , axi , AMBA-AXI	1	478	April 14, 2023
Can we have write data before address in AXI? UVM UVM , AMBA-AXI	2	1660	January 1, 2023
4KB concept in AXI SystemVerilog SystemVerilog , AMBA-AXI	1	814	August 30, 2022
In AXI, at what scenario can use out of order and outstanding transactions SystemVerilog SystemVerilog , AMBA-AXI , model-uvm-reference_model	2	2691	July 20, 2022
How does AXI/AHB protocols avoid race conditions SystemVerilog SystemVerilog , Race-condition , AHB , AMBA-AXI	1	887	May 7, 2021
Axi UVM UVM , AMBA-AXI	0	1051	February 10, 2021
AXI Interconnect in UVM UVM UVM , axi , AMBA-AXI , AXI-VIP	1	2189	August 30, 2019
Hold a register value until a control signal is seen SystemVerilog SystemVerilog , Cookbook-Registers , AMBA-AXI	1	796	July 15, 2019
Transfer size in AMBA AXI SystemVerilog SystemVerilog , BURST , AMBA-AXI , Number_Bytes , Transfer-size , wrap_boundary	2	1946	February 8, 2018

Axi boundary calculation

Announcements

Announcements , AHB-burst , signal-width-calculation-assertions , axi-amba-protocol , AMBA-AXI , AXI-VIP

3

9710

June 5, 2025

AXI UVM question/advice

UVM

UVM , AMBA-AXI

0

223

January 30, 2025

Data width is 128 bits but only LSB 32-bits are valid

UVM

UVM , AMBA-AXI

11

2352

October 2, 2024

AXI narrow transfer

SystemVerilog

OVM , axi-driver , axi , axi-amba-protocol , AMBA-AXI , AXI-VIP , AXI4-Stream

0

473

August 27, 2024

I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave

UVM

SystemVerilog , UVM , AMBA-AXI , AMBA-VIP , model-uvm-reference_model , coverage-UVM-module-class

3

830

August 24, 2023

AXI based Q

UVM

UVM , System-Verilog , axi , AMBA-AXI

1

478

April 14, 2023

Can we have write data before address in AXI?

UVM

UVM , AMBA-AXI

2

1660

January 1, 2023

4KB concept in AXI

SystemVerilog

SystemVerilog , AMBA-AXI

1

814

August 30, 2022

In AXI, at what scenario can use out of order and outstanding transactions

SystemVerilog

SystemVerilog , AMBA-AXI , model-uvm-reference_model

2

2691

July 20, 2022

How does AXI/AHB protocols avoid race conditions

SystemVerilog

SystemVerilog , Race-condition , AHB , AMBA-AXI

1

887

May 7, 2021

Axi

UVM

UVM , AMBA-AXI

0

1051

February 10, 2021

AXI Interconnect in UVM

UVM

UVM , axi , AMBA-AXI , AXI-VIP

1

2189

August 30, 2019

Hold a register value until a control signal is seen

SystemVerilog

SystemVerilog , Cookbook-Registers , AMBA-AXI

1

796

July 15, 2019

Transfer size in AMBA AXI

SystemVerilog

SystemVerilog , BURST , AMBA-AXI , Number_Bytes , Transfer-size , wrap_boundary

2

1946

February 8, 2018