I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave
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3
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349
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August 24, 2023
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AXI based Q
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1
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361
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April 14, 2023
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Can we have write data before address in AXI?
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2
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873
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January 1, 2023
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4KB concept in AXI
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1
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539
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August 30, 2022
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In AXI, at what scenario can use out of order and outstanding transactions
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2
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2009
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July 20, 2022
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How does AXI/AHB protocols avoid race conditions
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1
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761
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May 7, 2021
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Axi
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0
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931
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February 10, 2021
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Data width is 128 bits but only LSB 32-bits are valid
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7
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1823
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July 8, 2020
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Axi boundary calculation
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2
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9020
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February 19, 2020
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AXI Interconnect in UVM
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1
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1840
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August 30, 2019
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Hold a register value until a control signal is seen
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1
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726
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July 15, 2019
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Transfer size in AMBA AXI
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2
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1723
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February 8, 2018
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