Topics tagged AMBA-AXI

Topic	Replies	Views	Activity
I am trying to understand the way I can write a UVM scoreboard for a DUT(arbiter) with multiple masters and one slave like 3 AXI masters-> DUT-> AXI slave UVM SystemVerilog , UVM , AMBA-AXI , AMBA-VIP , model-uvm-reference_model , coverage-UVM-module-class	3	490	August 24, 2023
AXI based Q UVM UVM , System-Verilog , axi , AMBA-AXI	1	417	April 14, 2023
Can we have write data before address in AXI? UVM UVM , AMBA-AXI	2	1072	January 1, 2023
4KB concept in AXI SystemVerilog SystemVerilog , AMBA-AXI	1	628	August 30, 2022
In AXI, at what scenario can use out of order and outstanding transactions SystemVerilog SystemVerilog , AMBA-AXI , model-uvm-reference_model	2	2211	July 20, 2022
How does AXI/AHB protocols avoid race conditions SystemVerilog SystemVerilog , Race-condition , AHB , AMBA-AXI	1	817	May 7, 2021
Axi UVM UVM , AMBA-AXI	0	973	February 10, 2021
Data width is 128 bits but only LSB 32-bits are valid UVM UVM , AMBA-AXI	7	1939	July 8, 2020
Axi boundary calculation Announcements Announcements , AHB-burst , signal-width-calculation-assertions , axi-amba-protocol , AMBA-AXI , AXI-VIP	2	9190	February 19, 2020
AXI Interconnect in UVM UVM UVM , axi , AMBA-AXI , AXI-VIP	1	1942	August 30, 2019
Hold a register value until a control signal is seen SystemVerilog SystemVerilog , Cookbook-Registers , AMBA-AXI	1	761	July 15, 2019
Transfer size in AMBA AXI SystemVerilog SystemVerilog , BURST , AMBA-AXI , Number_Bytes , Transfer-size , wrap_boundary	2	1805	February 8, 2018